Publications

112. C. Nitta, M. Farrens, and Venkatesh Akella, DCOF- AN ARBITRATION FREE DIRECTLY CONNECTED OPTICAL FABRIC, IEEE Emerging and Selected Topics in Circuits and Systems, Vol. 2 Issue 2, pages 169-182, 2012

111. K. MacDonald, C. J. Nitta, M. Farrens, and Venkatesh Akella, PDG_GEN: A METHODOLOGY FOR FAST AND ACCURATE SIMULATION OF ONCHIP NETWORKS, IEEE Transactions on Computers, Issue 99, 2012

110.  C. Nitta, M. Farrens, and Venkatesh Akella, DCAF-A DIRECTLY CONNECTED ARBITRATION-FREE PHOTONIC CROSSBAR FOR ENERGY-EFFICIENT COMPUTING, 26th IEEE Parallel & Distributed Processing Symposium (IPDPS), pags 1144-1155, 2012

109.  Roberto Proietti, Christopher J. Nitta, Yawei Yin, Venkatesh Akella, and S.J.B. Yoo, SCALABILITY AND PERFORMANCE OF A DISTRIBUTED AWGR-BASED ALL-OPTICAL TOKEN ARCHITECTURE  in Optical Fiber Communication Conference (OFC), Paper OW3H.1 , March, 2013.

108.  Roberto Proietti, Yawei Yin, Runxiang Yu, Christopher Nitta, Xiaohui Ye, Venkatesh Akella, and S. J. B. Yoo, AN ALL OPTICAL TOKEN TECHNIQUE ENABLING A FULLY-DISTRIBUTED CONTROL PLANE IN AWGR-BASED OPTICAL INTERCONNECTS, in Journal of Lightwave Technology, Vol. 31, No. 3, pp. 414-422, February, 2013.

107.  Roberto Proietti, Yawei Yin, Runxiang Yu, Xiaohui Ye, Christopher NItta, Venkatesh Akella, and S. J. B. Yoo, ALL OPTICAL PHYSICAL LAYER NACK IN AWGR-BASED OPTICAL INTERCONNECTS, in IEEE Photonics Technology Letters, Vol. 24, No. 5, pp. 410-412, March, 2012

106. Roberto Proietti, Christopher J. Nitta, Yawei Yin, Runxiang Yu, S. J. B. Yoo, and Venkatesh Akella, SCALABLE AND DISTRIBUTED CONTENTION RESOLUTION IN AWGR-BASED DATA CENTER SWITCHES, IEEE Journal of Selected Topics in Quantum Electronics, 2012.

105.  Yawei Yin, Roberto Proietti, Xiaohui Ye, Christopher J. Nitta, Runxiang Yu, Ke Wen, Venkatesh Akella, and S. J. B. Yoo, LIONS: A LOW-LATENCY OPTICAL SWITCH FOR HIGH PERFORMANCE COMPUTING, IEEE of Selected Topics in Quantum Electronics, 2012.

104.  X. Ye, S.J.B. Yoo and V. Akella. AWGR-BASED OPTICAL TOPOLOGIES FOR SCALABLE AND EFFICIENT GLOBAL COMMUNICATION IN LARGE SCALE MULTIPROCESSORS SYSTEMS, IEEE/OSA Journal of Optical Communications and Networking, Vol. 4, No. 9, pp. 651-662, September, 2012.

103.  X. Chen and V. Akella. EXPLOITING DATA LEVEL PARALLELISM FOR ENERGY EFFICIENT IMPLEMENTATION OF LDPC DECODERS AND DCT ON A FPGA. ACM Transactions on Reconfigurable Technology and  Systems, 19 pages. 2011

102.  X. Ye, R. Proietti, Y. Yin, S.J.B. Yoo and V. Akella. BUFFERING AND FLOW CONTROL IN OPTICAL SWITCHES FOR HIGH PERFORMANCE COMPUTING. Journal of Optical Communications and Networking, Vol. 3, No. 8, pp. A59-A72, August, 2011

101.  X. Chen, J. Kang, S. Lin and V. Akella. HARDWARE IMPLEMENTATION OF A BACKTRACKING-BASED RECONFIGURABLE DECODER FOR LOWERING THE ERROR FLOOR OF QUASI-CYCLIC LDPC CODES. IEEE Transactions on Circuits and Systems-I, 13 pages. 2011

100.  X. Chen, S. Lin and V. Akella. EFFICIENT CONFIGURABLE DECODER ARCHITECTURE FOR NON-BINARY QUASI-CYCLIC LDPC CODES. IEEE Transactions on Circuits and Systems-I, 10 pages, 2011

99.  R. Proietti, R. Yu, S. Yin, Y. Yin, X. Ye, V. Akella and S.J.B. Yoo. ALL-OPTICAL NACK FOR FAST PACKET RETRANSMISSION IN AWGR-BASED OPTICAL SWITCHES. European Conference on Optical Communications Technical Digest, Geneva, Sept. 2011.

98. C. Nitta, M. Farrens, and V. Akella, RESILIENT MICRORING RESONATOR BASED PHOTONIC NETWORKS, International Symposium on Microarchitecture (MICRO), pages 95-104, 2011

97. Y. Yin, X. Ye, R. Proietti, V. Akella and S.J.B. Yoo. EXPERIMENTAL DEMONSTRATION OF END-TO-END MESSAGE PASSING FOR HPC SYSTEMS THROUGH A HYBRID OPTICAL SWITCH. European Conference on Optical Communications Technical Digest, Paper Tu6.K5, Geneva, Sept, 3 pages. 2011

96.  C. Nitta, K. Macdonald, M. Farrens and V. Akella. INFERRING PACKET DEPENDENCIES TO IMPROVE TRACE BASED SIMULATION OF ONCHIP NETWORKS. Proceedings of the Fifth IEEE/ACM International Symposium on Networks on Chip (NOCS), May, 153-160. 2011

95.  R. Proietti, X. Ye, Y. Yin, A. Potter, R. Yu, J. Kurumida, V. Akella and S.J.B. Yoo. 40 Gb/s 8×8 LOW-LATENCY OPTICAL SWITCH FOR DATA CENTERS. Proceedings of the OSA Optical Fiber Communications Conference (OFC/INFOEC), Paper OMV4, March, 3 pages. 2011

94.  X. Ye, A. Potter, Y. Yin, R. Proietti, S.J.B. Yoo and V. Akella. FAST BARRIER SYNCHRONIZATION WITH AWGR-BASED OPTICAL SWITCH IN HIGH-PERFORMANCE AND PARALLEL COMPUTING. Proceedings of the OSA Optical Fiber Communications Conference (OFC/INFOEC), Paper OWH3, March, 3 pages. 2011

93.  X. Ye, V. Akella and S.J.B. Yoo. COMPARATIVE STUDIES OF ALLOPTICAL VS. ELECTRICAL VS. HYBRID SWITCHES IN DATACOM AND IN TELECOM NETWORKS. Proceedings of the OSA Optical Fiber Communications Conference (OFC/INFOEC), Paper OThQ4, 2011

92.  C. Nitta, M. Farrens and V. Akella. ADDRESSING SYSTEM-LEVEL TRIMMING ISSUES IN ON-CHIP NANOPHOTONIC NETWORKS. Proceedings of the IEEE 17th International Symposium on High Performance Computer Architecture (HPCA) , 122-131. 2011

91. X. Chen, J. Kang, S. Lin and V. Akella. MEMORY SYSTEM OPTIMIZATION FOR FPGA-BASED IMPLEMENTATION OF QUASICYCLIC LDPC CODES DECODERS. IEEE Transactions on Circuits and Systems – I, 58(1): 98-111.

90. E. Jung, Y. Wang, I. Prilepov, F. Maker, X. Liu and V. Akella. USERPROFILE-DRIVEN COLLABORATIVE BANDWIDTH SHARING ON MOBILE PHONES. Proceedings of the 1st ACM Workshop on Mobile Cloud Computing & Services: Social Networks and Beyond, San Francisco, June, 9 pages.2010

89. E. Jung, F. Maker, T.L. Cheung, X. Liu and V. Akella. MARKOV DECISION PROCESS (MDP) FRAMEWORK FOR SOFTWARE POWER OPTIMIZATION USING CALL PROFILES ON MOBILE PHONES. Journal of Design Automation for Embedded Systems, 14(2): 131-159. 2010

88.  Y. Yin, X. Ye, D. Ding, S. Johnson, V. Akella and S.J.B. Yoo. TOWARDS SCALABLE, CONTENTION-FREE DATA CENTER NETWORKING WITH ALL-OPTICAL SWITCHING FABRIC. Proceedings of the OSA Photonics in Switching Conference, Paper PMC2, Monterey, July, 3 pages. 2010

87.  C. Nitta, M. Farrens and V. Akella. AN INVESTIGATION INTO SYSTEM-LEVEL TRIMMING ISSUES IN ON-CHIP NANOPHOTONIC NETWORKS. Proceedings of the Workshop on the Interaction between Nanophotonic Devices and Systems, Atlanta, GA, Dec, 2 pages. 2010

86.  X. Ye, Y. Yin, S.J.B. Yoo, P. Mejia. R. Proietti and V. Akella. DOS – A SCALABLE OPTICAL SWITCH FOR DATACENTERS. Proceedings of the ACM/IEEE Symposium on Architechure for Networking and Communications Systems (ANCS), 12 pages. 2010

85. Y. Yin, R. Proietti, X. Ye, S.J.B. Yoo and V. Akella. EXPERIMENTAL DEMONSTRATION OF OPTICAL PROCESSOR-MEMORY INTERCONNECTION. Proceedings of the International Conference on Advanced Intelligence and Awareness Internet, 213-216, 2010

84. X. Chen, S. Lin and V. Akella. QSN–A SIMPLE CIRCULAR-SHIFT NETWORK FOR RECONFIGURABLE QUASI-CYCLIC LDPC DECODERS. IEEE Transactions on Circuits and Systems – II, 57(10): 782-786, 2010

83. H. Yang, Z. Pan, V. Akella, C.-N. Chuah and S.J.B. Yoo. OPTICAL ROUTER CONTROL ARCHITECTURE AND CONTENTION RESOLUTION ALGORITHMS CAPABLE OF ASYNCHRONOUS, VARIABLE-LENGTH PACKET SWITCHING. IEEE/OSA Journal of Optical Communications and Networking, 2(9): 745-759. 2010

82.  R. Proietti, Y. Yin, J. Kurumida, X. Ye, B. Guan, R. Yu, V. Akella and S.J.B. Yoo. EXPERIMENTAL DEMONSTRATION OF 8×8 10 Gb/s LOW-LATENCY AND CONTENTION-LESS WAVELENGTH ROUTING OPTICAL SWITCH FOR DATA CENTER NETWORKS. Proceedings of the 36th European Conference and Exhibition on Optical Communication, 2010

81.  X. Ye, Y. Yin, D. Ding, S. Johnson, V. Akella and S.J.B Yoo. ASSESSMENT OF OPTICAL SWITCHING IN DATA CENTER NETWORKS. Proceedings of the Conference on Optical Fiber Communication, Paper JWA63,2010

80.  P. V. Mejia, R. Amirtharajah, M. K. Farrens and V. Akella. PERFORMANCE EVALUATION OF A MULTICORE SYSTEM WITH OPTICALLY CONNECTED MEMORY MODULES. Proceedings of the 4th ACM/IEEE International Symposium on Networks-on-Chip (NOCS), 215-222. 2010

79.  T.l. Cheung, K. Okamoto, F. Maker, X. Liu and V. Akella. MARKOV DECISION PROCESS (MDP) FRAMEWORK FOR OPTIMIZING SOFTWARE ON MOBILE PHONES. Proceedings of the 7th ACM International Conference on Embedded Software, 11-20. 2009

78.  X. Chen, Q. Huang, S. Lin and V. Akella. FPGA-BASED LOWCOMPLEXITY HIGH-THROUGHPUT TRI-MODE DECODER FOR QUASI-CYCLIC LDPC CODES. Proceedings of the 47th IEEE Annual Allerton Conference, 600-606, 2009

77.  L. Zhou, S. S. Djordjevic, R. Proietti, D. Ding S. J. Ben Yoo, R. Amirtharajah and V. Akella. DESIGN AND EVALUATION OF AN ARBITRATION-FREE PASSIVE OPTICAL CROSSBAR FOR ON-CHIP INTERCONNECTION NETWORKS. Applied Physics A, Special Issue on Photonic Interconnects, Guest Editor: Chongcheng Fan, Lars Thylen, Stan Williams, Alan Willner, and Ming Wu, (95) 1111-1118, 2009

76.  L. Zhou, K. Kashiwagi, K. Okamoto, R. P. Scott, N.K. Fontaine, D. Ding, V. Akella, and S. J. B. Yoo. TOWARDS ATHERMAL OPTICALLYINTERCONNECTED COMPUTING SYSTEM USING SLOTTED SILICON MICRORING RESONATORS AND RF PHOTONIC COMB GENERATION. Applied Physics A, Special Issue on Photonic Interconnects, Guest Editor: Chongcheng Fan, Lars Thylen, Stan Williams, Alan Willner, and Ming Wu, (95) 1101-1109, 2009

75. Xi. Chen, J. Kang, S. Lin and V. Akella. ACCELERATING FPGA-BASED EMULATION OF QUASI-CYCLIC LDPC CODES WITH VECTOR PROCESSING. Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE), 1530-1535, 2009

74. S. J. Ben Yoo, V. Akella, R. Amirtharajah, B. Baas, K. Bergman, S. Fan, J. S. Harris, Jr., M. Lipson, D. A. B. Miller, and J. Shalf. BALANCED COMPUTING WITH NANOPHOTONIC INTERCONNECTS (INVITED). Proceedings of the 21st Annual Meeting of the IEEE Lasers & Electro- Optics Society, Newport Beach, 368-369, 2008

73. R. Geyer J. Oliver, R. Amirtarajah, V. Akella, and F. Chong. MICROCHIP REUSE: ENVIRONMENTAL RATIONALE AND DESIGN IMPLICATIONS. Proceedings of the IEEE International Symposium Electronics and the Environment, (ISEE 2008), 2 pages, 2008

72. A. Hadke, E. A. Benavides, R. Amirtharajah, M. Farrens, and V. Akella. DESIGN AND EVALUATION OF AN OPTICAL CPU/ DRAM INTERCONNECT. Proceedings of the 26th International Conference on Computer Design (ICCD), 492-497, 2008

71. A. Hadke, E. A. Benavides, S. J. Ben Yoo, R. Amirtharajah, and V. Akella. OCDIMM: SCALING THE DRAM MEMORY WALL USING WDM BASED OPTICAL INTERCONNECTS. Proceedings of 16th IEEE Symposium on High Performance Interconnects, 57-63, 2008

70. J. Oliver, R. Amirtharajah, V. Akella and F. T. Chong. CREDIT-BASED DYNAMIC RELIABILITY MANAGEMENT USING ONLINE WEAROUT DETECTION. Proceedings of the ACM Computing Frontiers Conference, 139-148, 2008

69. J. Y. Oliver, R. Amirtharajah, V. Akella, R. Geyer and F. T. Chong. LIFE CYCLE AWARE COMPUTING: REUSING SILICON TECHNOLOGY. Computer, 40(12): 56-61, 2007

68. Haijun Yang, Zuqing Zhu, Bo Xiang, Wei Jiang, Venkatesh Akella, Chen-Nee Chuah, and S. J. Ben Yoo, “Design and experimental demonstration of novel optical router controller capable of asynchronous, variable-length packet switching and contention resolution,” in Technical Digest of IEEE/OSA Optical Fiber Communication Conference, paper no. JWA76, 2007.

67. Haijun Yang, Zhong Pan, Venkatesh Akella, Chen-Nee Chuah, and S. J. Ben Yoo, “Efficient contention resolution algorithms for recirculation multicast based optical router switch architecture,” in International Conference on Photonics in Switching 2006 (PS2006), Herakleion (Crete), Greece, October 2006.

66. Haijun Yang, Venkatesh Akella, Chen-Nee Chuah, and S. J. Ben Yoo, “Design of novel optical router controller and arbiter capable of asynchronous, variable length packet switching,” in International Conference on Photonics in Switching 2006 (PS2006), Herakleion (Crete), Greece, October 2006.

65. John Oliver, Diana Franklin, Fred Chong and Venkatesh Akella “Using Application Bisection Bandwidth to Guide Tile Size Selection for Synchroscalar Tile Based Architecture”, Transaction on High-Performance Embedded Architectures and Compilers, Volume 1, December 2006.

64. John Oliver and Ravishankar Rao and Michael Brown and Jennifer Mankin and Diana Franklin and Frederic T. Chong and Venkatesh Akella, “Tile Size Selection for Low-Power Tile-Based Architectures”, ACM International Conference on Computing Frontiers, CF06, Ischia, Italy, May 2006

63. Ravishankar Rao, Justin Wenck, Diana Franklin, Raj Amirtharajah and Venkatesh Akella, “Segmented Bitline Cache”, High Performance Computing – HiPC 2006, 13th International Conference, Bangalore, India, December 18-21, 2006, Proceedings. Lecture Notes in Computer Science 4297 Springer 2006, ISBN 3-540-68039-X

62.  Ravishankar Rao, Justin Wenck, Diana Franklin, Raj Amirtharajah and Venkatesh Akella, “Exploiting Non-Uniform Memory Access Patterns through Bit-line Segmentation” ACM SIGMICRO Letters Volume 24, Number 1, 2006,

61.  Junqiang Hu, Zhong Pan, Zuqing Zhu, Haijun Yang, Venkatesh Akella, and S. J. Ben Yoo, ” First experimental demonstration of combined multicast and unicast video streaming over an optical-label switching network,” in IEEE/OSA Optical Fiber Communication Conference (IEEE/OSA OFC 2006), paper OTuJ2, Anaheim, California, March 2006.

60.  Darshan D. Thaker, Diana Franklin, Venkatesh Akella, Frederic T. Chong, RELIABILITY REQUIREMENTS OF CONTROL, ADDRESS, AND DATA OPERATIONS IN ERROR TOLERANT APPLICATIONS, First Workshop on Architectural Reliability, Barcelona, 2005.

59. J. Oliver, R. Rao, D. Franklin, F. Chong and V. Akella. SYNCHROSCALAR: EVALUATION OF AN EMBEDDED, MULTI-CORE ARCHITECTURE FOR MEDIA APPLICATIONS. Journal of Embedded Systems: Special Issue on Multi-Core Architectures, December 2005.

58. Z. Pan, H. Yang, J. Yang, J. Hu, Z. Zhu, J. Cao, K. Okamoto, S. Yamano, V. Akella, and S.-J. B. Yoo. ADVANCED OPTICAL-LABEL ROUTING SYSTEM SUPPORTING MULTICAST, OPTICAL TTL, AND MULTIMEDIA APPLICATIONS. ” IEEE/OSA Journal of Lightwave Technology, vol. 23, no. 10, pp. 3270-3281, October 2005.

57.  Venkatesh Akella and Soheil Ghiasi OVERCOMING VON NEUMANN TO SAVE MOORE, High Performance Embedded Computing Workshop, MIT Lincoln Laboratories, September, 2005

56.  Venkatesh Akella, M. van der schaar and Wen Fu Kao, PROACTIVE ENERGY OPTIMIZATION ALGORITHMS FOR WAVELET-BASED VIDEO CODECS ON POWER-AWARE PROCESSORS, International Conference on Multimedia & Expo, ICME 2005

55.  G. Landge M. van der Schaar and Venkatesh Akella, COMPLEXITY METRIC DRIVEN ENERGY OPTIMIZATION FRAMEWORK FOR IMPLEMENTING MPEG-21 SCALABLE VIDEO DECODERS, Acoustics, Speech, and Signal Processing, 2005. Proceedings. (ICASSP ’05). IEEE International Conference on Volume 2, March 18-23, 2005 Page(s):1141– 1144

54.  Gouri Landge, Mihaela van der Schaar, Venkatesh Akella, GENERIC MODELING OF COMPLEXITY FOR MOTION-COMPENSATED WAVELET VIDEO DECODERS in Image and Video Communications and Processing 2005, Volume 5685, No. 5685, Edited-by Amir Said, John G. Apostolopoulos, pages 347-353.

53.  Junqiang Hu, Zhong Pan, Zuqing Zhu, Haijun Yang, Tinoosh Mohsenin, Venkatesh Akella, S. J. Ben Yoo, FIRST EXPERIMENTAL DEMONSTRATION OF IP-CLIENT-TO-IP-CLIENT VIDEO STREAMING APPLICATION OVER AN ALL-OPTICAL LABEL-SWITCHING NETWORK WITH EDGE ROUTERS, Optical Fiber Communication Conference, paper OFP2, 2005.

52.  Haijun Yang, Venkatesh Akella, Chen-Nee Chuah, and S. J. Ben Yoo, SCHEDULING OPTICAL PACKETS IN WAVELENGTH, TIME AND SPACE DOMAINS FOR ALL-OPTICAL PACKET SWITCHING ROUTERs, IEEE International Conference on Communications (ICC) 2005, Seoul, Korea, May 2005.

51.  Fei Xue, Zhong Pan, Haijun Yang, Jinqiang Yang, Jing Cao, Okamoto K, Kamei S, Venkatesh Akella, Yoo SJB. DESIGN AND EXPERIMENTAL DEMONSTRATION OF A VARIABLE-LENGTH OPTICAL PACKET ROUTING SYSTEM WITH UNIFIED CONTENTION RESOLUTION. Journal of Lightwave Technology, vol.22, no.11, Nov. 2004, pp.2570-81

50. John Oliver, Venkatesh Akella and F. T. Chong. EFFICIENT ORCHESTRATION OF SUBWORD PARALLELISM IN SIMD ARCHITECTURES. Proceedings of the Sixteenth ACM Symposium on Parallelism in Algorithms and Architectures, June 27-30, 2004, Barcelona, Spain, pages 225-234

49. Zhong Pan, Haijun Yang, Zuqing Zhu, Jing Cao, Venkatesh Akella, Steven Butt, S. J. Ben Yoo, DEMONSTRATION OF VARIABLE-SIZE PACKET CONTENTION RESOLUTION AND PACKET FORWARDING IN AN OPTICAL-LABEL SWITCHING ROUTER, IEEE Photonics Technology Letters, vol. 16, no. 4, July 2004.

48. Mihaela van der Schaar, D. Turaga and Venkatesh Akella, RATE-DISTORTION-COMPLEXITY ADAPTIVE VIDEO COMPRESSION AND STREAMING Image Processing, 2004. ICIP ’04. 2004 International Conference on,Volume 3, 24-27 Oct. 2004 Page(s):2051 – 2054 Vol. 3

47.  Gouri Landge, Mihaela van der Schaar, Venkatesh Akella, COMPLEXITY ANALYSIS OF SCALABLE MOTION-COMPENSATED WAVELET VIDEO DECODERS Proc. SPIE Vol. 5558, p. 444-453, Applications of Digital Image Processing XXVII; Andrew G. Tescher; Ed. (9 pages)

46.  John Oliver, Ravishankar Rao, Paul Sultana, Jedidiah Crandall, Erik Czernikowski, Leslie W. Jones IV, Diana Keen, Venkatesh Akella, and Frederic T. Chong SYNCHROSCALAR: A MULTIPLE CLOCK DOMAIN POWER AWARE TILE-BASED EMBEDDED PROCESSOR, International Symposium on Computer Architecture, ISCA, June 2004

45.  John Oliver, Ravishankar Rao, P. Sultana , J. Crandall, E.. Czernikowski, LW Jones IV, D. Copsey, D. Keen, Venkatesh Akella, Chong FT. DESIGN OF A TILE-BASED EMBEDDED ARCHITECTURE. Power-Aware Computer Systems. Third International Workshop, PACS 2003. Revised Papers (Lecture Notes in Computer Science Vol.3164). Springer-Verlag. 2004, pp.73-85. Berlin, Germany.

44.  Z. Pan, H. Yang, Z. Zhu, J. Cao, V. Akella, S. Butt, and S.-J. B. Yoo. EXPERIMENTAL DEMONSTRATION OF VARIABLE-SIZE PACKET CONTENTION RESOLUTION AND SWITCHING IN AN OPTICAL-LABEL SWITCHING ROUTER. IEEE/OSA Optical Fiber Communication Conference Technical Digest, 3 pp. (2004)

43.  Z. Pan, M. Y. Jeon, Y. Bansal, J. Cao, J. Taylor, S. J. B. Yoo, V. Akella, K. Okamoto, and S. Kamei. PACKET-BY-PACKET CONTENTION RESOLUTION IN AN OPTICAL-LABEL SWITCHING SYSTEM WITH 2R REGENERATION. IEEE/OSA Conference on Lasers and Electro-optics Technical Digest, paper CThX6, 2003

42.  J. Taylor, Y. Bansal, M. Y. Jeon, Z. Pan, J. Cao, V. J. Hernandez, Z. Zhu, Z. Wang, S. J. B. Yoo, V. Akella, T. Nady, G. Goncher, K. Ervin, K. Boyer, and B. Davies. DEMONSTRATION OF IP CLIENT-TO-IP CLIENT PACKET TRANSPORT OVER AN OPTICAL LABEL-SWITCHING NETWORK WITH EDGE ROUTERS. Proceedings of the 29th European Conference on Optical Communication, ECOC-IOOC, Vol. 1, pp. 20-21. 2003

41.  J. Cao, M. Jeon, Z. Pan, Y. Bansal, Z. Wang, Z. Zhu, V. Hernandez, J. Taylor, V. Akella, S. Yoo, K. Okamoto, and S. Kamei. ERROR-FREE MULTI-HOP CASCADED OPERATION OF OPTICAL LABEL SWITCHING ROUTERS WITH ALL-OPTICAL LABEL SWAPPING. In the IEEE/OSA Optical Fiber Communication Conference Technical Digest, pp. 791-792. 2003

40.  M. Y. Jeon, Z. Pan, J. Cao, Y. Bansal, J. Taylor, Z. Wang, V. Akella, K. Okamoto, S. Kamei, J. Pan, and S. J. B. Yoo. DEMONSTRATION OF ALL-OPTICAL PACKET SWITCHING ROUTERS WITH OPTICAL LABEL SWAPPING AND 2R REGENERATION FOR SCALABLE OPTICAL LABEL SWITCHING NETWORK APPLICATIONS. IEEE/OSA Journal of Lightwave Technology, Vol. 21, No. 11, pp. 2723-2733. 2003

39.  F. Xue, Z. Pan, Y. Bansal, J. Cao, M. Jeon, K. Okamoto, S. Kamei, V. Akella, and S. J. B. Yoo. END-TO-END CONTENTION RESOLUTION SCHEMES FOR AN OPTICAL PACKET SWITCHING NETWORK WITH ENHANCED EDGE ROUTERS. IEEE/OSA Journal of Lightwave Technology, Vol. 21, No. 11, pp. 2595-2604. 2003

38.  J. Oliver and V. Akella. IMPROVING DSP PERFORMANCE WITH A SMALL AMOUNT OF FIELD PROGRAMMABLE LOGIC. Proceedings of the 13th International Conference on Field-Programmable Logic and Applications, FPL 2003, LNCS 2779, P.Y.K. Cheung, et al (Eds.), pp. 520-532. 2003

37.  S. J. B. Yoo, F. Xue, Y. Bansal, J. Taylor, Z. Pan, J. Cao, M. Jeon, T. Nady, G. Goncher, K. Boyer, K. Okamoto, S. Kamei, and V. Akella. HIGH-PERFORMANCE OPTICAL-LABEL SWITCHING PACKET ROUTERS AND SMART EDGE ROUTERS FOR THE NEXT-GENERATION INTERNET. IEEE Journal of Selected Areas in Communications, Vol. 21, No. 7, pp. 1041-1051 2003

36.  Z. Pan, M. Y. Jeon, Y. Bansal, J. Cao, J. Taylor, V. Akella, S. Kamei, K. Okamoto, and S. J. B. Yoo. PACKET-BY-PACKET WAVELENGTH, TIME, SPACE-DOMAIN CONTENTION RESOLUTION IN AN OPTICAL-LABEL SWITCHING ROUTER WITH 2R REGENERA-TION. IEEE Photonics Technology Letters, Vol. 15, No. 9, pp. 1312-1314. 2003

35.  Z. Pan, J. Cao, Y. Bansal, V.K. Tsui, S.K.H. Fong, Y. Zhang, J. Taylor, H.J. Lee, M. Jeon, V. Akella, S.J.B. Yoo, K. Okamoto, and S. Kamei. ALL-OPTICAL PROGRAMMABLE TIME-SLOT-INTERCHANGER USING OPTICAL-LABEL SWITCHING WITH TUNABLE WAVELENGTH CONVERSION AND N AND N ARRAYED WAVEGUIDE GRATING ROUTERS. In Optical Fiber Conference, OFC,  2002

34.  S.J.B. Yoo, Y. Bansal, Z. Pan, J. Cao, V.K. Tsui, S.K.H. Fong, Y. Zhang, J. Taylor, H.J. Lee, M. Jeon, and V. Akella. OPTICAL-LABEL BASED PACKET ROUTING SYSTEM WITH CONTENTION RESOLUTION IN WAVELENGTH, TIME, AND SPACE DOMAINS. In Optical Fiber Conference, OFC, 2002

33.  T. Werner and V. Akella. AN ASYNCHRONOUS SUPERSCALAR ARCHITECTURE FOR EXPLOITING INSTRUCTION-LEVEL PARALLEISM. Proceedings of the International Symposium on Advanced Research on Asynchronous Circuits and Systems, ASYNC 2001, March, pp. 140-151.

32. N. Raghavan, V. Akella, and S. Bakshi. AUTOMATION INSERTION OF GATED CLOCKS AT REGISTER TRANSFER LEVEL. Proceedings of the Twelfth International Conference on VLSI Design, IEEE Computer Society, pp. 48-54. 1999

31. R. Pandey, V. Akella, and P. Devanbu. SUPPORT FOR EVOLUTION OF THE SYSTEMS THROUGH SOFTWARE COMPOSITION. Proceedings of the International Workshop on the Principles of Software Evolution, pp. 1-6, 1998

30. V. Akella, N. H. Vaidya, and G. R. Redinbo. ASYNCHRONOUS COMPARISON-BASED DECODERS FOR DELAY-INSENSITIVE CODES. IEEE Transaction on Computers, Vol. 47, No. 7, pp. 802-811. 1998

29. D. Johnson, V. Akella, and B. Stott. MICROPIPELINED SYNCHRONOUS DISCRETE COSINE TRANSFORM (DCT/IDCT) PROCESSOR. IEEE Transactions on VLSI Systems, Vol. 6, No. 4, pp. 731-740. 1998

28. D. Johnson and V. Akella. DESIGN AND ANALYSIS OF ASYNCHRONOUS ADDER. IEE Proceedings for Computers and Digital Techniques, Vol. 145, No. 1, pp. 1-8. 1998

27. K. Maheswar and V. Akella,. PGA-STC: A PROGRAMMABLE GATE ARRAY FOR SELF-TIMED CIRCUITS. International Journal of Electronics, Vol. 84, No. 3, pp. 255-267. 1998

26. T. Werner and V. Akella. ASYNCHRONOUS PROCESSOR SURVEY. IEEE Computer, Vol. 30, No. 11, pp. 67-76. 1997

25.  V. Akella, N. Vaidya, R. Redinbo. LIMITATIONS OF VLSI IMPLEMENTATION OF DELAY-INSENSITIVE CODES. Proceedings of Annual Symposium on Fault Tolerant Computing, pp. 208-217. 1996

24.  T. Werner, V. Akella. COUNTERFLOW PIPELINE BASED DYNAMIC INSTRUCTION SCHEDULING. Proceedings of Second International Symposium on Advanced Research in Asynchronous Circuits and Systems, pp. 69-79. 1996

23.  B. Stott, D. Johnson, and V. Akella. ASYNCHRONOUS 2-D DISCRETE COSINE TRANSFORM CORE PROCESSOR. Proceedings of the International Conference on Computer Design (ICCD-95). 1995

22.  P. Kudva, G. Gopalakrishnan, and V. Akella. HIGH LEVEL SYNTHESIS OF ASYNCHRONOUS CIRCUIT TARGETING STATE MACHINE CONTROLLERS. International Conference on Hardware Description Languages (CHDL 95), pp. 605-610. 1995

21.  P. Reddy and V. Akella. DESIGN OF AN ADAPTIVE SMART CARD WITH IN-LAB EXPERIMENTS. Proceedings of the IEEE-IEE Vehicle Navigation and Information Systems Conference, 6 pages. 1995

20.  P. Kudva and V. Akella. A TECHNIQUE FOR ESTIMATING POWER IN ASYNCHRONOUS CIRCUITS. First International Symposium on Asynchronous Circuits and Systems, pp. 166-175. 1994

19.  P. Kudva, G. Gopalakrishnan, and V. Akella. PERFORMANCE ANALYSIS OF ASYNCHRONOUS CIRCUITS USING TIMED PETRI NETS. International Conference on Computer Design (ICCD-94), pp. 166-175 1994

18.  P. Kudva and V. Akella. TESTING TWO PHASE TRANSITION SIGNALING BASED SELF-TIMED CIRCUITS IN A SYNTHESIS ENVIRONMENT. Proceedings of the Seventh International Symposium on High-Level Synthesis, pp. 103-111. 1994

17.  G. Gopalakrishnan and V. Akella. HIGH-LEVEL OPTIMIZATIONS IN COMPILING PROCESS DESCRIPTIONS TO ASYNCHRONOUS CIRCUITS. Journal of VLSI Signal Processing, Vol. 7, pp. 33-45., 1994

16. V. Akella and G. Gopalakrishnan. SPECIFICATION AND VALIDATION OF CONTROL-INTENSIVE IC’S IN hopCP. IEEE Transactions on Software Engineering, Vol. 20, No. 6, pp. 405-423,1994

15.  V. Akella and G. Gopalakrishnan. CFSIM: A CONCURRENT COMPILED- CODE FUNCTIONAL SIMULATOR FOR hopCP. International Journal in Computer Simulation, Vol. 4, No. 4, pp. 375-393, 1993

14.  G. Gopalakrishnan and V. Akella. A TRANSFORMATIONAL APPROACH TO ASYNCHRONOUS HIGH-LEVEL SYNTHESIS. Proceedings of the International Conference on Very Large Scale Integration (VLSI 93) 1993

13.  G. Gopalakrishnan and V. Akella. SPECIFICATION, SIMULATION, AND SYNTHESIS OF SELF-TIMED CIRCUITS. Proceedings of the 26th Annual Hawaii International Conference on System Sciences, Vol. I, pp. 399-408. 1993

12.  J-L. Sung and V. Akella. IMPLEMENTING DELAY INSENSITIVE SELF-TIMED CIRCUITS WITH SINGLE-RAIL DATA SIGNALS. ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 11 pages. 1993

11. G. Gopalakrishnan and V. Akella. VLSI ASYNCHRONOUS SYSTEMS: SPECIFICATION AND SYNTHESIS. Microprocessors & Microsystems, Vol. 16, No. 10, pp. 517-527. 1992

10.  V. Akella and G. Gopalakrishnan. SHILPA: A HIGH-LEVEL SYNTHESIS SYSTEM FOR SELF-TIMED CIRCUITS. Proceedings of the International Conference on Computer Aided Design (ICCAD), pp. 587-591. 1992

9.  Venkatesh Akella and G. Gopalakrishnan. FLOW ANALYSIS TECHNIQUES FOR THE SYNTHESIS OF EFFICIENT ASYNCHRONOUS CIRCUITS. Proceedings of the Second ACM/SIGDA Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 13 pages. 1992

8.  Venkatesh Akella and G. Gopalakrishnan. FROM PROCESS-ORIENTED FUNCTIONAL SPECIFICATIONS TO EFFICIENT ASYNCHRONOUS CIRCUITS. Proceedings of the Fifth International Conference on VLSI. 1992

7.  Venkatesh Akella and G. Gopalakrishnan. HIERARCHICAL ACTION REFINEMENT: A METHODOLOGY FOR COMPILING ASYNCHRONOUS CIRCUITS FROM A CONCURRENT HDL. Proceedings of the Tenth International Symposium on Computer Hardware Description Languages and their Applications, CHDL-91, pp. 351-369. 1991

6.  Venkatesh Akella and G. Gopalakrishnan. HIGH LEVEL TEST GENERATION VIA PROCESS COMPOSITION. Designing Correct Circuits, edited by Geraint Jones and Mary Sheeran. Springer-Verlag (London) ISBN 3-540-19659-5, pp. 99-119. 1991

5. G. Gopalakrishnan, P. Jain, V. Akella, L. Josephson, and W -Y Kuo. COMBINING VERIFICATION AND SIMULATION. Proceedings of the 1991 UC Santa Cruz Conference on Advanced Research in VLSI, pp. 323-339,1991

4. G. Gopalakrishnan, N. Mani, and V. Akella. A DESIGN VALIDATION SYSTEM FOR SYNCHRONOUS HARDWARE BASED ON A PROCESS MODEL: A CASE STUDY. Proceedings of the IMEC-IFIP International Workshop on Formal VLSI Specification and Synthesis VLSI Design Method-I, pp. 227-247. 1989

3. G. Gopalakrishnan, R. Fujimoto, and V. Akella. HOP: A PROCESS MODEL FOR SYNCHRONOUS HARDWARE; SEMANTICS AND EXPERIMENTS IN PROCESS COMPOSITION. Integration, the VLSI Journal, Vol. 8, pp. 209-247. 1989

2. G. Gopalakrishnan, R. Fujimoto, V. Akella, N. Mani, and K. Smith. SPECIFICATION-DRIVEN DESIGN OF CUSTOM HARDWARE IN HOP. Current Trends in Hardware Verification and Automated Theorem Proving, edited by Birtwistle and Subrahmanyam, Chapter 3, pp. 128-170. 1989

1. G. Gopalakrishnan, N. Mani, and V. Akella. PARALLEL COMPOSITION OF LOCKSTEP SYNCHRONOUS PROCESSES FOR HARDWARE VALIDATION: DIVIDE-AND-CONQUER COMPOSITION. Proceedings of the Workshop on Automatic Verification Methods for Finite State Systems, pp. 375-382. 1989

 

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