{"id":17,"date":"2013-02-26T20:32:40","date_gmt":"2013-02-26T20:32:40","guid":{"rendered":"http:\/\/faculty.engineering.ucdavis.edu\/template\/?page_id=17"},"modified":"2013-07-01T02:40:15","modified_gmt":"2013-07-01T02:40:15","slug":"publications","status":"publish","type":"page","link":"https:\/\/faculty.engineering.ucdavis.edu\/farrens\/publications\/","title":{"rendered":"Publications"},"content":{"rendered":"<h3>List of Refereed Publications<\/h3>\n<ul>\n<li>V. Ahuja, D. Ghosal and M. Farrens, <a href=\"http:\/\/american.cs.ucdavis.edu\/publications\/tba.html\"> &#8220;Minimizing the Data Transfer Time Using Multicore End-sSystem Aware Blow Bifurcation&#8221; <\/a>, <i>12th IEEE\/ACM International Symposium on Cluster, Cloud and Grid Computing (CCGrid)<\/i>, Ottowa, Canada (May 13-16, 2012), pp. (to appear).<\/li>\n<li>C. Nitta, M. Farrens and V. Akella, <a href=\"http:\/\/american.cs.ucdavis.edu\/publications\/ipdps12dcaf.pdf\"> &#8220;DCAF &#8211; A Directly Connected Arbitration-Free Photonic Crossbar for Energy-Efficient High Performance Computing&#8221;<\/a>, <i>26th IEEE International Parallel and Distributed Processing Symposium<\/i>, Shanghai, China (May 21-25, 2012), pp. (to appear).<\/li>\n<li>C. Nitta, M. Farrens and V. Akella, <a href=\"http:\/\/american.cs.ucdavis.edu\/publications\/MICRO44_Christopher_Nitta.pdf\"> &#8220;Resilient Microring Resonator Based Photonic Networks&#8221;<\/a>, <i>Proceedings of the 44th Annual IEEE\/ACM International Symposium on Microarchitecture<\/i>, Porto Alegre, Brazil (Dec 3-7, 2011), pp. 95-104<\/li>\n<li>C. Nitta, K. Macdonald, M. Farrens and V. Akella, <a href=\"http:\/\/american.cs.ucdavis.edu\/publications\/nocs11.pdf\"> &#8220;Inferring packet dependencies to improve trace based simulation of on-chip networks &#8220;<\/a>, <i> Proceedings of the 5th Annual IEEE\/ACM International Symposium on Networks on Chips<\/i>, Pittsburgh, PA (May 1-4, 2011), pp. 153-160.<\/li>\n<li>C. Nitta, M. Farrens and V. Akella, <a href=\"http:\/\/american.cs.ucdavis.edu\/publications\/hpca2011.pdf\"> &#8220;Addressing System-Level Trimming Issues in OnChip Nanophotonic Networks&#8221;<\/a>, <i>Proceedings of the 17th International IEEE Symposium on High Performance Computer Architecture<\/i>, San Antonio, TX (Feb 12-16, 2011), pp. 122-131<\/li>\n<li>P. V. Mejia, R. Amirtharajah, M. Farrens and V. Akella, &#8220;Performance Evaluation of a Multicore System with Optically Connected Memory Modules&#8221;, <i>Fourth ACM\/IEEE International Symposium on Networks-on-Chip<\/i> , Grenoble, France (May 3-6, 2010), pp. 215-222 .<\/li>\n<li>A. Hadke, T. Benavides, V. Akella, R. Amirtharajah and M. Farrens, &#8220;Design and Evaluation of an Optical CPU-DRAM Interconnect&#8221;, <i>Proceedings of the IEEE International Conference on Computer Design (ICCD): Green Computing<\/i>, Lake Tahoe, CA (October 12-15, 2008), pp. 492-497.<\/li>\n<li>C. Nitta and M. Farrens, &#8220;Techniques for Increasing Effective Data Bandwidth&#8221;, <i>Proceedings of the IEEE International Conference on Computer Design (ICCD): Green Computing<\/i>, Lake Tahoe, CA (October 12-15, 2008), pp. 492-497.<\/li>\n<li>P. Congdon and M. Farrens, &#8220;Packet Prediction for Speculative C ut-Through Switching&#8221;, <i>ACM\/IEEE Symposium on Architectures for Networking and Communications Systems<\/i>, San Jose, CA (November 6-7, 2008), pp. 514-519.<\/li>\n<li>H. Lee, G. Tyson and M. Farrens, &#8220;Improving Bandwidth Utilization using Eager Writeback&#8221;, <i>Journal of Instruction Level Parallelism<\/i>, vol. 4 (to appear) (January 2002)<\/li>\n<li>M. Oskin, F. Chong, and M. Farrens, &#8220;Using Statistical and Symbolic Simulation for Microprocessor Evaluation&#8221;, <i>Journal of Instruction Level Parallelism<\/i>, vol. 3 (to appear) (September 2001)<\/li>\n<li>H. Lee, G. Tyson and M. Farrens, <a href=\"http:\/\/huron.cs.ucdavis.edu\/matt\/publications\/lee.pdf\"> &#8220;Eager Writeback &#8211; a Technique for Improving Bandwidth Utilization&#8221;<\/a>, <i>Proceedings of the 33rd Annual International Symposium on Microarchitecture<\/i>, Monterey, CA (December 10-13, 2000), pp. 11-21<\/li>\n<li>K. Rich and M. Farrens, <a href=\"http:\/\/huron.cs.ucdavis.edu\/matt\/publications\/decoupled.europar2k.pdf\"> The Decoupled-Style Prefetch Architecture&#8221;<\/a>, <i>Proceedings of the 6th International Euro-Par Conference<\/i>, Munich, Germany (August 28-September 1, 2000), pp. 989-993.<\/li>\n<li>K. Rich and M. Farrens, <a href=\"http:\/\/huron.cs.ucdavis.edu\/matt\/publications\/partitioning.europar2k.pdf\"> &#8220;Code Partitioning in Decoupled Compilers&#8221;<\/a>, <i>Proceedings of the 6th International Euro-Par Conference<\/i>, Munich, Germany (August 28-September 1, 2000), pp. 1008-1017.<\/li>\n<li>M. Oskin, F. Chong and M. Farrens, <a href=\"http:\/\/huron.cs.ucdavis.edu\/matt\/publications\/p71-oskin.pdf\"> &#8220;HLS:\u00a0 Combining Statistical and Symbolic Simulation to Guide Microprocessor Designs&#8221;<\/a>, <i>Proceedings of the 27th Annual International Symposium on Computer Architecture<\/i>, Vancouver, BC (June 12-14, 2000), pp. 71-82.<\/li>\n<li>P. Sallee, M. Haungs and M. Farrens, <a href=\"http:\/\/huron.cs.ucdavis.edu\/matt\/publications\/transrate.ps\"> &#8220;Branch Transistion Rate:\u00a0 A New Metric for Improved Branch Classification Analysis&#8221;<\/a>, <i>Proceedings of the 6th International IEEE Symposium on High Performance Computer Architecture<\/i> , Toulouse, France (January 10-12, 2000), pp. 241-250.<\/li>\n<li>M. Oskin, J. Hensley, D. Keen, F. Chong, M. Farrens and A. Chopra, <a href=\"http:\/\/huron.cs.ucdavis.edu\/matt\/publications\/oskin.pdf\"> &#8220;Exploiting ILP in Page-based Intelligent Memory&#8221;<\/a>, <i>Proceedings of the 32nd Annual International Symposium on Microarchitecture<\/i>, Haifa, Israel (November 16-18, 1999), pp. 208-218.<\/li>\n<li>J. Rivers, E. Tam, G. Tyson, E. Davidson and M. Farrens, <a href=\"http:\/\/huron.cs.ucdavis.edu\/matt\/publications\/ICS98.ps.gz\"> &#8220;Utilizing Reuse Information in Data\u00a0 Cache Management&#8221;<\/a>, <i>Proceedings of the 12th ACM International Conference on Supercomputing<\/i>&#8220;, Melbourne, Australia (July 13-17, 1998), pp. 449-456.<\/li>\n<li>G. Tyson, M. Farrens, J. Matthews and A. Pleszkun, &#8220;Managing Data Caches using Selective Cache Line Replacement&#8221;, <i>International Journal of Parallel Processing<\/i>, vol. 25, no. 3 (June 1997), pp. 213-242.<\/li>\n<li>G. Tyson and M. Farrens, <a href=\"http:\/\/huron.cs.ucdavis.edu\/matt\/publications\/ijpp96.ps\"> &#8220;Evaluating the Effects of Predicated Execution on Branch Prediction&#8221; <\/a> , <i>International Journal of Parallel Processing, <\/i>vol. 23, no. 1 (1996)<\/li>\n<li>G. Tyson, M. Farrens, J. Matthews, and A. Pleszkun,<a href=\"http:\/\/huron.cs.ucdavis.edu\/matt\/publications\/Micro28.95.ps\"> &#8220;A Modified Approach to Data Cache Management&#8221; <\/a>, <i>Proceedings of the 28th Annual International Symposium on Microarchitecture <\/i>Ann Arbor, MI (Nov 29-Dec 1, 1995).<\/li>\n<li>M. Farrens, G. Tyson, and A. Pleszkun,<a href=\"http:\/\/huron.cs.ucdavis.edu\/matt\/publications\/ISCA.94.ps\"> &#8220;A Study of Single-Chip Processor\/Cache Organizations for Large Numbers of Transistors&#8221; <\/a>, <i>Proceedings of the 21st Annual International Symposium on Computer Architecture, <\/i>Chicago, IL (April 18-21, 1994).<\/li>\n<li>G. Tyson, M. Farrens, <a href=\"http:\/\/huron.cs.ucdavis.edu\/matt\/publications\/IJPP.94.ps\"> &#8220;Code Scheduling for Multiple Instruction Stream Architectures&#8221; <\/a>, <i> International Journal of Parallel Processing, <\/i>vol. 22, no. 3 (1994)<\/li>\n<li>M. Farrens, P. Nico and P. Ng, <a href=\"http:\/\/huron.cs.ucdavis.edu\/matt\/publications\/Micro26.93a.ps\"> &#8220;A Comparison of Superscalar and Decoupled Access\/Execute Architectures&#8221; <\/a> , <i>Proceedings of the 26th Annual International Symposium on Microarchitecture, <\/i>Austin, Texas (December 1-3, 1993)<\/li>\n<li>G. Tyson and M. Farrens, <a href=\"http:\/\/huron.cs.ucdavis.edu\/matt\/publications\/Micro26.93b.ps\"> &#8220;Techniques for Extracting Instruction Level Parallelism on MIMD Architectures&#8221; <\/a>, <i>Proceedings of the 26th Annual International Symposium on Microarchitecture, <\/i>Austin, Texas (December 1-3, 1993)<\/li>\n<li>G. Tyson, M. Farrens and A. Pleszkun, <a href=\"http:\/\/huron.cs.ucdavis.edu\/matt\/publications\/Micro25.92a.ps\"> &#8220;MISC: A Multiple Instruction Stream Computer&#8221; <\/a>, <i>Proceedings of the 25th Annual International Symposium on Microarchitecture, <\/i>Portland, Oregon (December 1-4, 1992)<\/li>\n<li>A. Park, M. Farrens and G. Tyson, <a href=\"http:\/\/huron.cs.ucdavis.edu\/matt\/publications\/MICRO25a.ps\"> &#8220;Modifying VM Hardware to Reduce Address Pin Requirements&#8221; <\/a>, <i>Proceedings of the 25th Annual International Symposium on Microarchitecture, <\/i>Portland, Oregon (December 1-4, 1992)<\/li>\n<li>M. Farrens, A. Park, R. Fanfelle, P. Ng and G. Tyson, <a href=\"http:\/\/huron.cs.ucdavis.edu\/matt\/publications\/ISCA.92.ps\"> &#8220;A Partitioned Translation Lookaside Buffer Appraoch to Reducing Address Bandwidth&#8221; <\/a>, <i>Proceedings of the 19th Annual International Symposium on Computer Architecture, <\/i>Queensland, Australia (May 19-21, 1992)<\/li>\n<li>M. Farrens, A. Park and A. Woodruff, <a href=\"http:\/\/huron.cs.ucdavis.edu\/matt\/publications\/IPPS.92.ps\"> &#8220;CCHIME: A Cache Coherent Hybrid Interconnected Memory Extension&#8221; <\/a>, <i> Proceedings of the 6th International Parallel Processing Symposium, <\/i>Hollywood, California (March, 1992)<\/li>\n<li>M. Farrens, B. Wetmore and A. Woodruff, <a href=\"http:\/\/huron.cs.ucdavis.edu\/matt\/publications\/Supercomputing91.ps\"> &#8220;Alleviation of Tree Saturation in Multistage Interconnection Networks&#8221; <\/a> , <i>Proceedings of Supercomputing &#8217;91, <\/i>Albuquerque, New Mexico (November, 1991)<\/li>\n<li>J. Becker, A. Park and M. Farrens, <a href=\"http:\/\/huron.cs.ucdavis.edu\/matt\/publications\/Micro24b.ps\"> &#8220;An Analysis of the Information Content of Address Reference Streams&#8221; <\/a> , <i>Proceedings of the 24th Annual International Symposium on Microarchitecture, <\/i>Albuquerque, New Mexico (November, 1991)<\/li>\n<li>M. Farrens and A. Park, <a href=\"http:\/\/huron.cs.ucdavis.edu\/matt\/publications\/Micro24.91a.ps\"> &#8220;Workload and Implementation Considerations for Dynamic Base Register Caching&#8221; <\/a>, <i>Proceedings of the 24th Annual International Symposium on Microarchitecture, <\/i>Albuquerque, New Mexico (November, 1991)<\/li>\n<li>M. Farrens and A. Pleszkun, <a href=\"http:\/\/american.cs.ucdavis.edu\/publications\/ISCA.91a.ps\"> &#8220;Strategies for Achieving Improved Processor Throughput&#8221; <\/a>, <i>Proceedings of the 18th Annual International Symposium on Computer Architecture, <\/i> Toronto, Canada (May 27-30, 1991).<\/li>\n<li>M. Farrens and A. Park, <a href=\"http:\/\/american.cs.ucdavis.edu\/publications\/ISCA.91b.ps\"> &#8220;Dynamic Base Register Caching: A Technique for Reducing Address Bus Width&#8221; <\/a>, <i>Proceedings of the 18th Annual International Symposium on Computer Architecture, <\/i>Toronto, Canada (May 27-30, 1991).<\/li>\n<li>M. Farrens and A. Pleszkun, <a href=\"http:\/\/american.cs.ucdavis.edu\/publications\/Computer.pdf\"> &#8220;Implementation of the PIPE Processor&#8221; <\/a>, <i>Computer<\/i>, January 1991<\/li>\n<li>M. Farrens and A. Pleszkun, <a href=\"http:\/\/american.cs.ucdavis.edu\/publications\/HICSS91.ps\"> &#8220;Overview of the PIPE Processor Implementation&#8221; <\/a>, <i>Proceedings of the 24th Annual Hawaii International Conference on System Sciences, <\/i>Kapaa, Kauai (January 9-11, 1991).<\/li>\n<li>A. Park and M. Farrens, <a href=\"http:\/\/american.cs.ucdavis.edu\/publications\/Micro23.90a.ps\"> &#8220;Address Compression Through Base Register Caching&#8221; <\/a>, <i>Proceedings of the 23th Annual Symposium and Workshop on Microprogramming and Microarchitectures, <\/i>Orlando, Florida (November 1990)<\/li>\n<li>M. Farrens and A. Pleszkun, <a href=\"http:\/\/american.cs.ucdavis.edu\/publications\/Micro23.90b.pdf\"> &#8220;An Evaluation of Functional Unit Lengths for Single Chip Processors&#8221; <\/a> , <i>Proceedings of the 23th Annual Symposium and Workshop on Microprogramming and Microarchitectures, <\/i>Orlando, Florida (November 1990)<\/li>\n<li>M. Farrens and A. Pleszkun, <a href=\"http:\/\/american.cs.ucdavis.edu\/publications\/p234-farrens.pdf\"> &#8220;Improving the Performance of Small On-Chip Instruction Caches&#8221; <\/a>, <i> Proceedings of the 16th Annual International Symposium on Computer Architecture, <\/i>Jerusalem, Israel (June 1989).<\/li>\n<li>A. Pleszkun and M. Farrens, <a href=\"http:\/\/american.cs.ucdavis.edu\/publications\/VLSI.pdf\"> &#8220;An Instruction Cache Design for Use with a Delayed Branch&#8221; <\/a><i>Advanced Research in VLSI: Proceedings of the Fourth MIT Conference <\/i>, April 1986<\/li>\n<\/ul>\n<p>&nbsp;<\/p>\n<h3>List of Unrefereed Publications (Tech Reports)<\/h3>\n<ul>\n<li>Matthew Farrens,\u00a0 <a href=\"http:\/\/american.cs.ucdavis.edu\/publications\/teaching-wkshp.ps\"> &#8220;The Architecture Curriculum at UC-Davis&#8221;<\/a> , <i>IEEE Technical Committee on Computer Architecture,<\/i> February 1999, pp. 28-30.<\/li>\n<li>Matthew Farrens,\u00a0 <a href=\"http:\/\/american.cs.ucdavis.edu\/publications\/teaching-wkshp_long.ps\"> &#8220;The Architecture Curriculum at UC-Davis&#8221;<\/a> ,\u00a0 presented at the <i> Workshop on Computer Architecture Education<\/i>, held in conjunction with the <i>25th Annual International Symposium on Computer Architecture, <\/i> Barcelona, Spain, June 1998.<\/li>\n<li>Matthew Farrens, Timothy Heil, James E. Smith and Gary Tyson, <a href=\"http:\/\/american.cs.ucdavis.edu\/publications\/cse-97-18.ps\"> &#8220;Restricted Dual Path Execution&#8221; <\/a>, <i>Computer Science Department Technical Report CSE-97-18, <\/i>University of California at Davis, Davis, California (November 1997).<\/li>\n<li>Gary Tyson, Matthew Farrens, Kevin Rich, and Andrew Pleszkun, <a href=\"http:\/\/american.cs.ucdavis.edu\/publications\/cse-95-7.ps\"> &#8220;Reducing the Branch Penalty of Mispredicted Short Forward Branches&#8221; <\/a> , <i>Computer Science Department Technical Report CSE-95-7, <\/i>University of California at Davis, Davis, California (August 1995).<\/li>\n<li>Gary Tyson, Matthew Farrens, John Matthews, and Andrew Pleszkun, <a href=\"http:\/\/american.cs.ucdavis.edu\/publications\/cse-95-6.ps\"> &#8220;A New Approach to Cache Management&#8221; <\/a>, <i>Computer Science Department Technical Report CSE-95-6, <\/i>University of California at Davis, Davis, California (August 1995).<\/li>\n<li>M. Farrens, G. Tyson and A. Pleszkun, <a href=\"http:\/\/american.cs.ucdavis.edu\/publications\/cse-92-24.ps\"> &#8220;A Study of Single-Chip Processor\/Cache Organizations for Large Numbers of Transistors&#8221; <\/a>, <i>Computer Science Department Technical Report CSE-92-24, <\/i>University of California at Davis, Davis, California (December 1992).<\/li>\n<li>G. Tyson, M. Farrens and A. Pleszkun, <a href=\"http:\/\/american.cs.ucdavis.edu\/publications\/MISC.tech.ps\"> &#8220;MISC: A Multiple Instruction Stream Computer&#8221; <\/a>, <i>Computer Science Department Technical Report CSE-92-23, <\/i>University of California at Davis, Davis, California (December 1992).<\/li>\n<li>M. Farrens, A. Park, R. Fanfelle, P. Ng and G. Tyson, <a href=\"http:\/\/american.cs.ucdavis.edu\/publications\/cse-91-37.ps\"> &#8220;A Partitioned Translation Lookaside Buffer Approach to Reducing Address Bandwidth&#8221; <\/a>, <i>Computer Science Department Technical Report CSE-91-37, <\/i>University of California at Davis, Davis, California (November 1991).<\/li>\n<\/ul>\n","protected":false},"excerpt":{"rendered":"<p>List of Refereed Publications V. Ahuja, D. Ghosal and M. Farrens, &#8220;Minimizing the Data Transfer Time Using Multicore End-sSystem Aware Blow Bifurcation&#8221; , 12th IEEE\/ACM International Symposium on Cluster, Cloud and Grid Computing (CCGrid), Ottowa, Canada (May 13-16, 2012), pp. (to appear). C. Nitta, M. Farrens and V. Akella, &#8220;DCAF \u2026 <a class=\"continue-reading-link\" href=\"https:\/\/faculty.engineering.ucdavis.edu\/farrens\/publications\/\"> Continue reading <span class=\"meta-nav\">&rarr; <\/span><\/a><\/p>\n","protected":false},"author":3,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"open","template":"template-twocolumns-left.php","meta":{"inline_featured_image":false,"ngg_post_thumbnail":0,"footnotes":""},"class_list":["post-17","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/faculty.engineering.ucdavis.edu\/farrens\/wp-json\/wp\/v2\/pages\/17","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/faculty.engineering.ucdavis.edu\/farrens\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/faculty.engineering.ucdavis.edu\/farrens\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/faculty.engineering.ucdavis.edu\/farrens\/wp-json\/wp\/v2\/users\/3"}],"replies":[{"embeddable":true,"href":"https:\/\/faculty.engineering.ucdavis.edu\/farrens\/wp-json\/wp\/v2\/comments?post=17"}],"version-history":[{"count":9,"href":"https:\/\/faculty.engineering.ucdavis.edu\/farrens\/wp-json\/wp\/v2\/pages\/17\/revisions"}],"predecessor-version":[{"id":231,"href":"https:\/\/faculty.engineering.ucdavis.edu\/farrens\/wp-json\/wp\/v2\/pages\/17\/revisions\/231"}],"wp:attachment":[{"href":"https:\/\/faculty.engineering.ucdavis.edu\/farrens\/wp-json\/wp\/v2\/media?parent=17"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}