{"id":17,"date":"2013-02-26T20:32:40","date_gmt":"2013-02-26T20:32:40","guid":{"rendered":"http:\/\/faculty.engineering.ucdavis.edu\/template\/?page_id=17"},"modified":"2020-06-22T20:42:45","modified_gmt":"2020-06-22T20:42:45","slug":"publications","status":"publish","type":"page","link":"https:\/\/faculty.engineering.ucdavis.edu\/oklobzija\/publications\/","title":{"rendered":"Publications"},"content":{"rendered":"\n\n\n
1970 to 1979<\/strong><\/p>\n
    \n
  1. \n
      \n
    1. V. G. Oklobdzija and N. Konjevic,\u00a0“Spectroscopy Of Axisymmetric Plasma Sources”<\/a>,\u00a0Proceedings of the Eleventh International Conference on Phenomena in Ionized Gases<\/i>, p. 449, 1973.<\/li>\n
    2. V. G. Oklobdzija and N. Konjevic,\u00a0“Refractive-Ray Bending In Axially-Symmetric Plasma Sources”<\/a>,\u00a0Proceedings of the International Conference on the Physics of Ionized Gases<\/i>, 1974.<\/li>\n
    3. V. G. Oklobdzija and N. Konjevic, “Refractive-Ray Bending In Axially-Symmetric Plasma Sources”,\u00a0Journal of Quantitative Spectroscopy and Radiative Transfer<\/i>, Vol. 14, pp. 389-394, 1974.<\/li>\n<\/ol>\n<\/li>\n<\/ol>\n

      1980 to 1989<\/strong><\/p>\n

        \n
      1. \n
          \n
        1. V. G. Oklobdzija,\u00a0“Up\/Down Display Counter Counts Over Pos\/Neg Range”<\/a>,\u00a0Digital Design<\/i>, pp. 94-95, 1981.<\/li>\n
        2. V. G. Oklobdzija and M. D. Ercegovac, “Testability Enhancement Of VLSI Using Circuit Structures”<\/a>,\u00a0Proceedings of IEEE International Conference on Circuits and Computers, ICCC\u00a0<\/i>’82, pp. 198-201, 1982.<\/li>\n
        3. V. G. Oklobdzija and M. D. Ercegovac,\u00a0“An On-Line Square Root Algorithm”<\/a>,\u00a0IEEE Transactions on Computers<\/i>, Vol. C-31, No. 1, pp. 70-75, 1982.<\/li>\n
        4. V. G. Oklobdzija,\u00a0“Design Note. Opto-Isolated RS-232 Interface Achieves High Data Rate”<\/a>,\u00a0Electronics<\/i>, Vol. 55, No. 1, p. 175, 1982.<\/li>\n
        5. V. G. Oklobdzija,\u00a0“Improving Testability By Using Additional Circuits”<\/a>,\u00a0Proceedings of the Seventeenth Asilomar Conference on Circuits, Systems and Computers<\/i>, pp. 118-123, 1983.<\/li>\n
        6. J. P. Roth, V. G. Oklobdzija and J. F. Beetem,\u00a0“Test Generation For FET Switching Circuits”<\/a>,\u00a0Proceedings of the International Test Conference<\/i>, pp. 59-62, 1984.<\/li>\n
        7. V. G. Oklobdzija and P. G. Kovijanic,\u00a0“On Testability Of CMOS-Domino Logic”<\/a>,\u00a0Proceedings FTCS-14 : 14th IEEE International Conference on Fault- Tolerant Computing<\/i>, pp. 50-55, 1984.<\/li>\n
        8. V. G. Oklobdzija and E. R. Barnes,\u00a0“Some Optimal Schemes For ALU Implementation In VLSI Technology”<\/a>,\u00a0Proceedings of the 7th Symposium on Computer Arithmetic ARITH-7<\/i>, pp. 2-8. Reprinted in\u00a0Computer Arithmetic<\/i>, E. E. Swartzlander, (editor), Vol. II, pp. 137-142, 1985.<\/li>\n
        9. V. G. Oklobdzija and R. K. Montoye, “Design-Performance Trade-Offs In CMOS Domino Logic”,\u00a0Proceedings of the Custom Integrated Circuits Conference<\/i>, pp. 334-337, 1985.<\/li>\n
        10. V. G. Oklobdzija and R. K. Montoye,\u00a0“Design-Performance Trade-Offs In CMOS-Domino Logic”<\/a>,\u00a0IEEE Journal of Solid State Circuits<\/i>, Vol. SC-21, No. 2, pp. 304-306, 1986.<\/li>\n
        11. V. G. Oklobdzija, N. M. Marinovic and L. Roytman,\u00a0“Single-Chip Architecture For Real-Time Computation Of The Wigner Distribution Of Acoustic Signals”<\/a>,\u00a0Proceedings of the 21st Asilomar Conference on Signals, Systems and Computers<\/i>, pp. 939-943, 1987.<\/li>\n
        12. V. G. Oklobdzija and E. R. Barnes,\u00a0“On Implementing Addition in VLSI Technology”<\/a>,\u00a0IEEE Journal of Parallel and Distributed Computing<\/i>, No. 5, pp. 716-728, 1988.<\/li>\n
        13. V. G. Oklobdzija,\u00a0“Architecture For Single-Chip ASIC Processor With Integrated Floating Point Unit”<\/a>,\u00a0Proceedings of the 21st Hawaii International Conference on System Sciences<\/i>, pp. 1-9, 1988. (Best Paper award)<\/li>\n
        14. V. M. Marinovic, V. G. Oklobdzija and L. Roytman,\u00a0“VLSI Architecture Of A Real-Time Wigner Distribution Processor For Acoustic Signals”<\/a>,\u00a0Proceedings of the International Conference on Acoustics, Speech, and Signal Processing<\/i>, V4.7, pp. 2112-2115, 1988.<\/li>\n
        15. V. G. Oklobdzija and G. Grohosky,\u00a0“Architectural Study For An Integrated Fixed And Floating-Point VLSI-ASIC Processor”<\/a>, COMPEURO-’88,\u00a0IEEE Symposium on Circuits and Systems<\/i>, pp. 108-115, 1988.<\/li>\n
        16. V. G. Oklobdzija,\u00a0“Simple And Efficient CMOS Circuit For Fast VLSI Adder Realization”<\/a>,\u00a0Proceedings of the International Symposium on Circuits and Systems<\/i>, pp. 1-4, 1988.<\/li>\n
        17. V. G. Oklobdzija,\u00a0“Issues In CPU-Coprocessor Communication And Synchronization”<\/a>, EUROMICRO ’88,\u00a0Fourteenth Symposium, Microprocessing and Microprogramming<\/i>, North-Holland Publishers, Vol. 24, pp. 695-700, 1988.<\/li>\n
        18. V. G. Oklobdzija,\u00a0“Rapid Turn-Around Design Style And Technology: Impact On Computer Architecture”<\/a>,\u00a0Proceedings of the 22nd Annual Hawaii International Conference on System Sciences<\/i>\u00a0(HICSS-22), Vol. 1, page 1, 1989.<\/li>\n<\/ol>\n<\/li>\n<\/ol>\n

          1990 to 1994<\/strong><\/p>\n

            \n
          1. \n
              \n
            1. B. D. Lee and V. G. Oklobdzija,\u00a0“Optimization And Speed Improvement Analysis Of Carry-Lookahead Adder Structure”<\/a>,\u00a0Proceedings of the 24th Asilomar Conference on Signals, Systems and Computers<\/i>, Vol. 2 of 2, pp. 918-922, 1990.<\/li>\n
            2. P. K. Chan, M. D. F. Schlag, C. D. Thomborson and V. G. Oklobdzija,\u00a0“Delay Optimization Of Carry-Skip Adders And Block Carry-Lookahead Adders”<\/a>,\u00a0Proceedings of the 10th IEEE Symposium on Computer Arithmetic, ARITH-10,\u00a0<\/i>pp. 1-11, 1991.<\/li>\n
            3. B. D. Lee and V. G. Oklobdzija,\u00a0“Improved CLA Scheme With Optimized Delay”<\/a>,\u00a0Journal of VLSI Signal Processing<\/i>, Vol. 3, No. 4, pp. 265-274, 1991.<\/li>\n
            4. A. Sah, D. C. Verma and V. G. Oklobdzija,\u00a0“A Study Of I\/O Architecture For High Performance Next Generation Computers”<\/a>,\u00a0Proceedings of the 2nd Symposium on High Performance Computing<\/i>, pp. 1-12, 1991.<\/li>\n
            5. N. M. Marinovic and V. G. Oklobdzija,\u00a0“VLSI Chip Architecture For Real-Time Ambiguity Function Computation”<\/a>,\u00a0Proceedings of the 25th Asilomar Conference on Signals, Systems and Computers<\/i>, 1991, 5 pages.<\/li>\n
            6. P. K. Chan, M. D. Schlag, C. D. Thomborson and V. G. Oklobdzija,\u00a0“Delay Optimization Of Carry-Skip Adders And Block Carry-Lookahead Adders Using Multidimensional Dynamic Programming”<\/a>,\u00a0IEEE Transactions on Computers<\/i>, Vol. 41, No. 8, pp. 920-930, 1992.<\/li>\n
            7. V. G. Oklobdzija,\u00a0“An Implementation Algorithm And Design Of A Novel Leading Zero Detector Circuit”<\/a>,\u00a026th IEEE Asilomar Conference on Signals, Systems and Computers<\/i>, Vol 1, pp. 391-395, 1992. (Invited paper)<\/li>\n
            8. V. G. Oklobdzija, D. Villeger, and T. Soulas,\u00a0“Considerations For Design Of A Complex Multiplier”<\/a>,\u00a026th IEEE Asilomar Conference on Signals, Systems and Computers, Asilomar<\/i>, Vol. 1, pp. 366-370, 1992. (Invited paper)<\/li>\n
            9. V. G. Oklobdzija,\u00a0“Algorithmic Design Of A Hierarchical And Modular Leading Zero Detector Circuit”<\/a>,\u00a0Electronics Letters<\/i>, Vol. 29, No. 3, pp. 283-284, 1992.<\/li>\n
            10. T. Soulas, D. Villeger and V. G. Oklobdzija,\u00a0“An ASIC Macro Cell Multiplier For Complex Numbers”<\/a>,\u00a0Proceedings of EURO-ASIC-93, the European (EDAC) Conference in ASIC Design<\/i>, 1993, 5 pages.<\/li>\n
            11. V. G. Oklobdzija, “Computer Arithmetic”,\u00a0The Electrical Engineering Handbook<\/i>, R. C. Dorf (Ed.), a Chapter, CRC Press, Inc., pp. 1858-1865, 1993.<\/li>\n
            12. V. G. Oklobdzija and D. Villeger,\u00a0“Multiplier Design Utilizing Improved Column Compression Tree And Optimized Final Adder In CMOS Technology”<\/a>,\u00a0Proceedings of the 1993 International Symposium on VLSI Technology, Systems and Applications<\/i>, pp. 209-212, 1993.<\/li>\n
            13. V. G. Oklobdzija,\u00a0“A Hierarchical And Modular Circuit Implementing Leading Zero Detector For A High-Performance Floating-Point Processor”<\/a>,\u00a0Proceedings of the 5th International Symposium on IC Technology, Systems, and Applications<\/i>, ISIC-93, Nanyang Technological University, Singapore, 1993, 2 pages.<\/li>\n
            14. V. G. Oklobdzija, D. Villeger, and T. Soulas,\u00a0“An Integrated Multiplier For Complex Numbers”<\/a>,\u00a0Journal of VLSI Signal Processing<\/i>, Vol. 7, No. 3, pp. 213-222, 1993.<\/li>\n
            15. V. G. Oklobdzija,\u00a0“An Algoritmic And Novel Design Of A Leading Zero Detector Circuit: Comparison With Logic Synthesis”<\/a>,\u00a0IEEE Transactions on VLSI Systems<\/i>, Vol. 2, No. 1, pp. 124-128, 1993.<\/li>\n
            16. D. Villeger and V. G. Oklobdzija,\u00a0“Analysis Of Booth Encoding Efficiency In Parallel Multipliers Using Compressors For Reduction Of Partial Products”<\/a>,\u00a0Proceedings of the 27th Asilomar Conference on Signals, Systems and Computers<\/i>, pp. 781-784, 1993.<\/li>\n
            17. D. Villeger and V. G. Oklobdzija,\u00a0“Evaluation Of Booth Encoding Techniques For Parallel Multiplier Implementation”<\/a>,\u00a0Electronics Letters<\/i>, Vol. 29, No. 23, pp. 2016-2017, 1993.<\/li>\n
            18. V. G. Oklobdzija,\u00a0“New ECL Gate In BiFET Process”<\/a>,\u00a0Electronics Letters<\/i>, Vol. 29, No. 23, pp. 2029-2030, 1993.<\/li>\n
            19. M. Q. Le and V. G. Oklobdzija,\u00a0“Logic Synthesis For ASIC: A Guided Algorithmic Approach”<\/a>,\u00a0Proceedings of the 1994 International Conference on ASIC<\/i>, 1994, 4 pages.<\/li>\n
            20. A. de la Serna, M. A. Soderstrand and V. G. Oklobdzija,\u00a0“System For Rapid Prototyping Of Application Specific Signal Processors For ASIC Implementation”<\/a>,\u00a0Proceedings of the 1994 International Conference on ASIC Implementation<\/i>, pp. 157-160, 1994.<\/li>\n
            21. R. Hundal and V. G. Oklobdzija,\u00a0“Determination Of Optimal Sizes For A First And Second Level SRAM-DRAM On-Chip Cache Combination”<\/a>,\u00a0Proceedings of the 1994 International Conference on Computer Design<\/i>, 1994, 5 pages.<\/li>\n
            22. V. G. Oklobdzija,\u00a0“An ECL Gate With Improved Speed And Low Power In BiCMOS Process”<\/a>,\u00a0Proceedings of the 1994 Bipolar\/BiCMOS Circuits and Technology Meeting<\/i>, 1994, 4 pages.<\/li>\n
            23. V. G. Oklobdzija,\u00a0“Design And Analysis Of Fast Carry-Propagate Adder Under Non-Equal Input Signal Arrival Profile”<\/a>,\u00a0Proceedings of the 28th Asilomar Conference on Signals, Systems and Computers<\/i>, 1994, 4 pages.<\/li>\n
            24. R. H. Strandberg, J. C. Le Duc, Z-Y. Yang, L. G. Bustamante, V. G. Oklobdzija and M. Soderstrand,\u00a0“Reconfigurable Processor For Real-Time Adaptive Sample Rate Notch Filtering”<\/a>,\u00a0Proceedings of the 28th Asilomar Conference on Signals, Systems and Computers<\/i>, 1994, 4 pages.<\/li>\n
            25. R. H. Strandberg, J. C. Le Duc, L. G. Bustamante, V. G. Oklobdzija, and M. Soderstrand,\u00a0“Implementation Of Adapative Sample Rate Kwan-Martin Notch Filter Using Efficient Realizations Of Reciprocal And Squaring Circuit”<\/a>,\u00a0Proceedings of the 28th Asilomar Conference on Signals, Systems and Computers<\/i>, 1994, 5 pages.<\/li>\n<\/ol>\n<\/li>\n<\/ol>\n

              1995 to 1999<\/strong><\/p>\n

                \n
              1. \n
                  \n
                1. V. G. Oklobdzija and D. Villeger,\u00a0“Improving Multiplier Design By Using Improved Column Compression Tree And Optimized Final Adder In CMOS Technology”<\/a>,\u00a0IEEE Transactions on VLSI Systems<\/i>, Vol. 3, No. 2, June, 1995, 10 pages.<\/li>\n
                2. V. G. Oklobdzija, “Computer Organization: Architecture”,\u00a0The Engineering Handbook<\/i>, R. C. Dorf (Ed.), a Chapter, CRC Press, Inc., 1995, 20 pages.<\/li>\n
                3. M. N. Dorojevets and V. G. Oklobdzija,\u00a0“Multithreaded Decoupled Architecture”<\/a>,\u00a0International Journal of High-Speed Computing<\/i>, World Scientific Publisher, 16 pages, June, 1995.<\/li>\n
                4. V. G. Oklobdzija, D. Villeger, and S. S. Liu,\u00a0“A Method For Speed Optimized Partial Product Reduction And Generation Of Fast Parallel Multipliers Using An Algorithmic Approach”<\/a>,\u00a0IEEE Transactions on Computers<\/i>, Vol. 45, No. 3, March 1996.<\/li>\n
                5. K. J. Runge, P. Lee, J. Correa, R.T. Scalettar, V.G. Oklobdzija,\u00a0“Monte Carlo and Molecular Dynamic Simulations Using P4”<\/a>,\u00a0Proceedings of the 9th Int’l Parallel Processing Symposium<\/i>, Santa Barbara, California, April 24-29, 1995, 7 pages.<\/li>\n
                6. D. Maksimovic, V.G. Oklobdzija,\u00a0“Integrated Power Clock Generators for Low Energy Logic”<\/a>,\u00a0Proceedings of the 1995 Power Electronics Specialists Conference<\/i>, Atlanta, Georgia, June 18-22, 1995.<\/li>\n
                7. V. G. Oklobdzija and B. Duchene,\u00a0“Pass-Transistor Dual Value Logic For Low-Power CMOS”<\/a>,\u00a0Proceedings of the 1995 International Symposium on VLSI Technology<\/i>, Taipei, Taiwan, May 31-June 2nd, 1995.<\/li>\n
                8. C. Martel, V. G. Oklobdzija, R. Ravi and P. Stelling,\u00a0“Design Strategies For Optimal Multiplier Circuits”<\/a>,\u00a0Proceedings of the 12th IEEE Symposium on Computer Arithmetic<\/i>, Bath, ENGLAND, July 19-21,1995, 8 pages.<\/li>\n
                9. V. G. Oklobdzija, “Computers”,\u00a0The Engineering Handbook<\/i>, R. C. Dorf (Ed.), Introduction into Computers, a Chapter, CRC Press, Inc., 1995, 20 pages.<\/li>\n
                10. V. G. Oklobdzija,\u00a0“An ECL Gate with Improved Speed And Low-Power in BiCMOS Process”<\/a>,\u00a0Journal of Solid State Circuits<\/i>, January 1996.<\/li>\n
                11. V. G. Oklobdzija and B. Duchene,\u00a0“Logic Synthesis For Pass-Transistor Design”<\/a>,\u00a0IEEE International Conference on Solid-State and Integrated-Circuit Technology<\/i>, October 24-28, 1995, Beijing, China.<\/li>\n
                12. V. G. Oklobdzija and B. Duchene,\u00a0“Pass-Transistor Logic Family for High-Speed and Low Power CMOS”<\/a>,\u00a0Sixth International Symposium on IC Technology, Systems and Applications<\/i>, ISIC-95, Singapore, September 6-8, 1995.<\/li>\n
                13. D. Maksimovic, V. G. Oklobdzija,\u00a0“Clocked CMOS Adiabatic Logic with Single AC Power Supply”<\/a>,\u00a021st European Solid-State Circuits Conference<\/i>, September 19-21, 1995, Lille, FRANCE.<\/li>\n
                14. V. G. Oklobdzija, “Digital Systems”,\u00a0The Engineering Handbook<\/i>, R. C. Dorf (Ed.), Introduction into Digital Systems, Chapter, in press, CRC Press, Inc., 1995.<\/li>\n
                15. V. G. Oklobdzija and B. Duchene,\u00a0“Development and Synthesis Method for Pass-Transistor Logic Family for High-Speed and Low Power CMOS”<\/a>,\u00a038th Midwest Symposium on Circuits and Systems<\/i>, Rio de Janeriro, BRASIL, Auguts 13-16, 1995.<\/li>\n
                16. K. J. Runge, P. Lee, J. Correa, R. T. Seabettar, and V. G. Oklobdzija,\u00a0“Simulations of Interacting Many Body Systems Using P4”<\/a>,\u00a0Journal of High-Speed Computing<\/i>, World Scientific Publisher, 27 pages, August 1995.<\/li>\n
                17. P. Bonatto, V. G. Oklobdzija,\u00a0“Evaluation of Booth’s Algorithm for Implementation in Parallel Multipliers”<\/a>,\u00a0Twenty-Ninth Annual Asilomar Conference on signals, Systems and Computers<\/i>, Pacific Grove, California, October 29 – November 1, 1995.<\/li>\n
                18. Jean Noel, V. G. Oklobdzija,\u00a0“New Pipelined Architecture for DSP”<\/a>,\u00a0Twenty-Ninth Annual Asilomar Conference on signals<\/i>, Systems and Computers, Pacific Grove, California, October 29 – November 1, 1995.<\/li>\n
                19. V. G. Oklobdzija, P. Stelling,\u00a0“Design Strategies for the Final Adder in a Parallel Multiplier”<\/a>,\u00a0Twenty-Ninth Annual Asilomar Conference on signals, Systems and Computers<\/i>, Pacific Grove, California, October 29 – November 1, 1995.<\/li>\n
                20. V. G. Oklobdzija, “A Method for Generation of Fast Parallel Multipliers”,\u00a02nd International Conference on Massively Parallel Computing Systems<\/i>, May 6-9, 1996, Ischia, ITALY.<\/li>\n
                21. K. W. Current, V. G. Oklobdzija, D. Maksimovic,\u00a0“Low-Energy Logic Circuit Techniques for Multiple Valued Logic”<\/a>,\u00a0Second Int’l Symposium on Multiple-Valued Logic<\/i>, Santiago de Compostela, Spain, May 29-31, 1996.<\/li>\n
                22. P. Stelling , V. G. Oklobdzija,\u00a0“Design Strategies for Optimal Hybrid Final Adders in a Parallel Multiplier”<\/a>,\u00a0special issue on VLSI Arithmetic, Journal of VLSI Signal Processing,\u00a0<\/i>Kluwer Academic Publishers, Vol. 14, No. 3, December 1996.<\/li>\n
                23. R.H. Strandberg, J-C Le Duc, L.G. Bustamante, V. G. Oklobdzija, M. Soderstrand, “Efficient Realization of Squaring Circuit and Reciprocal used in Adaptive Sample Rate Notch Filters”,\u00a0special issue on VLSI Arithmetic<\/i>, Journal of VLSI Signal Processing, Kluwer Academic Publishers, Vol. 14, No. 3, December 1996.<\/li>\n
                24. V. G. Oklobdzija, Comments on “Leading-Zero Anticipatory Logic for High-Speed Floating Point Addition”,\u00a0IEEE Journal of Solid-State Circuits<\/i>, Vol. 32, No. 2, pp. 292-293, February 1997.<\/li>\n
                25. P. Stelling, V. G. Oklobdzija,\u00a0“Implementing Multiply-Accumulate Operation in Multiplication Time”<\/a>,\u00a0Thirteenth International Symposium on Computer Arithmetic<\/i>, Pacific Grove, California, July 5 – 9, 1997.<\/li>\n
                26. D. Maksimivic, V. G. Oklobdzija, B. Nikolic, K. W. Current,\u00a0“Design and Experimental Verification of a CMOS Adiabatic Logic with Single-Phase Power-Clock Supply”<\/a>,\u00a0Proceedings of the 40th Midwest Symposium on Circuits and Systems<\/i>, Sacramento, California, August 3-6, 1997.<\/li>\n
                27. D. Maksimovic, V. G. Oklobdzija, B. Nikolic, K. W. Current,\u00a0“Clocked CMOS Adiabatic Logic with Integrated Single-Phase Power-Clock Supply: Experimental Results”<\/a>,\u00a0International Symposium on Low Power Electronics and Design<\/i>, Monterey, California, August 18-20, 1997.<\/li>\n
                28. Paul F. Stelling and Vojin G. Oklobdzija,\u00a0“Optimal Designs for Multipliers and Multiply-Accumulators”<\/a>,\u00a0Proceedings of the 15th IMACS World Congress on Scientific Computation<\/i>, Modeling, and Applied Mathematics, Volume 4 Artificial Intelligence and Computer Science, Achim Sydow, editor, Wissenschaft and Technik Verlag, Berlin, August 1997, pp. 739-744.<\/li>\n
                29. B. Nikolic, V. G. Oklobdzija,\u00a0“A Single-Phase Clock High-Performance BiCMOS Latch”<\/a>,\u00a0Proceedings of the 7th International Symposium on IC Technology, Systems & Applications<\/i>, Singapore, September 10-12, 1997.<\/li>\n
                30. K. W. Current, V. G. Oklobdzija, D. Maksimovic, “On Adiabatic Multiple Valued Logic Circuits”,\u00a0Journal of Multiple Value Logic<\/i>, Vol. 2, Gordon and Breach Publishing, pp. 329-347, 1997.<\/li>\n
                31. V. G. Oklobdzija,\u00a0“Differential and Pass-Transistor CMOS Logic for High-Performance Systems”<\/a>,\u00a021st International IEEE Conference on Microelectronics<\/i>, September 14-17, 1997, Nis, Yugoslavia.<\/li>\n
                32. V. G. Oklobdzija, D. Maksimovic, F. C. Lin,\u00a0“Pass-Transistor Adiabatic Logic using Single Power-Clock Supply”<\/a>,\u00a0IEEE Transactions on Circuits and Systems-II<\/i>, Vol. 44, No. 10, pp. 842-846. October 1997.<\/li>\n
                33. V. G. Oklobdzija and B. Duchene,\u00a0“Synthesis Of High-Speed Pass-Transistor Logic”<\/a>,\u00a0IEEE Transactions on Circuits and Systems-II<\/i>, Vol. 44, No. 11, November 1997, 7 pages.<\/li>\n
                34. V. G. Oklobdzija,\u00a0“Differential and Pass-Transistor CMOS Logic for High-Performance Systems”<\/a>, reprinted from\u00a021st International IEEE Conference on Microelectronics<\/i>, Electronics, Vol. 1, No. 1, December 1997.<\/li>\n
                35. V. G. Oklobdzija, “Differential and Pass-Transistor CMOS Logic for High-Performance Systems”,\u00a0Microelectronics Journal<\/i>, Elsevier Publishing,\u00a0 March 1998.<\/li>\n
                36. P. Stelling, C. Martel, V. G. Oklobdzija, R. Ravi,\u00a0“Optimal Circuits For Parallel Multipliers”<\/a>,\u00a0IEEE Transactions on Computers<\/i>, Vol. 47, No. 3, pp. 273-285, March 98.<\/li>\n
                37. A. A. Farooqui, V. G. Oklobdzija,\u00a0“General Data-Path Organization of a MAC unit for VLSI Implementation of DSP Processors”<\/a>,\u00a01998 IEEE International Symposium on Circuits and Systems<\/i>, Monterey, California, May 31 – June 3, 1998.<\/li>\n
                38. B. Nikolic, V. G. Oklobdzija,\u00a0“Low Voltage BiCMOS TSPC Latch for High Performance Digital Systems”<\/a>,\u00a01998 IEEE International Symposium on Circuits and Systems<\/i>, May 31 – June 3, 1998, Monterey, California.<\/li>\n
                39. V. G. Oklobdzija,\u00a0“Architectural Tradeoffs for Low Power”<\/a>,\u00a0International Symposium on Computer Architecture<\/i>, Barcelona, SPAIN, June 27-July 1st, 1998.<\/li>\n
                40. V. Stojanovic, V. G. Oklobdzija, R. Bajwa,\u00a0“A Unified Approach in the Analysis of Latches and Flip-Flops for Low-Power Systems”<\/a>,\u00a0International Symposium on Low Power Electronics and Design<\/i>, Monterey, California, August 10-12, 1998.<\/li>\n
                41. V. Stojanovic, V. G. Oklobdzija, R. Bajwa,\u00a0“Comparative Analysis of Latches and Flip-Flops for High-Performance Systems”<\/a>,\u00a0International Conference on Computer Design<\/i>, Austin, Texas, October 5-7, 1998.<\/li>\n
                42. A. A. Farooqui, V. G. Oklobdzija,\u00a0“Early Branch Prediction Circuit For High Performance Digital Signal Processors”<\/a>,\u00a01998 IEEE Conference on Microelectronics<\/i>, Monastir, Tunisia, December 14-16, 1998.<\/li>\n
                43. B. Nikolic, V. Stojanovic, V.G. Oklobdzija, W. Jia, J. Chiu, M. Leung,\u00a0“Sense Amplifier-Based Flip-Flop”<\/a>,\u00a01999 IEEE International Solid-State Circuits Conference<\/i>, San Francisco, February 1999.<\/li>\n
                44. V. Stojanovic and V. G. Oklobdzija,\u00a0“Comaparative Analysis of Master-Slave Latches and Flip-Flops for High-Performance and Low-Power Systems”<\/a>,\u00a0IEEE Journal of Solid-State Circuits<\/i>, Vol. 34, No. 4, April 1999.<\/li>\n
                45. V. G. Oklobdzija, “Digital Arithmetic”,\u00a0Wiley Encyclopedia of Electrical and Electronics Engineering<\/i>, Vol. 5, Book Chapter, John Wiley publishing, 1999.<\/li>\n
                46. V. G. Oklobdzija, “Reduced Instruction Set Computing”,\u00a0Wiley Encyclopedia of Electrical and Electronics Engineering<\/i>, Vol. 18, Book Chapter, John Wiley publishing, 1999.<\/li>\n
                47. A. Farooqui, V. G. Oklobdzija,\u00a0“VLSI Implementation of Early Branch Prediction Circuits for High Performance Computing”<\/a>,\u00a09th Great Lakes VLSI conference<\/i>\u00a0(GLSVLSI 99), Ann Arbor, Michigan, March 4-6, 1999.<\/li>\n
                48. A. Farooqui, V. G. Oklobdzija, F. Chehrazi,\u00a0“64-Bit Media Adder”<\/a>,\u00a01999 IEEE International Symposium on Circuits and Systems<\/i>, Orlando, Florida, May 5-8, 1999.<\/li>\n
                49. A. Farooqui, V. G. Oklobdzija, F. Chehrazi,\u00a0“Multiplexer Based Adder for Media Signal Processing”<\/a>,\u00a01999 International Symposium on VLSI Technology, Systems, and Applications<\/i>, Taipei, Taiwan, June 8-10, 1999.<\/li>\n
                50. B. Nikolic, V. G. Oklobdzija,\u00a0“Design and Optimization of Sense Amplifier-Based Flip-Flops”<\/a>,\u00a025th European Solid-State Circuits Conference<\/i>, Duisburg, GERMANY, 21-23 September 1999.<\/li>\n
                51. F. Chehrazi, V. G. Oklobdzija, A. A. Farooqui, “Single-Cycle Throughput Multi-Media Multiplier”,\u00a0SONY Research Forum<\/i>\u00a0(SRF), Tokyo, JAPAN, October 1999.<\/li>\n
                52. B. Nikolic, M. Leung, L. Fu, V.G. Oklobdzija, R. Yamasaki,\u00a0“Reduced-Complexity Sequence Detection for E2<\/sup>PR4 Magnetic Recording Channel”<\/a>,\u00a0Proceedings of Global Telecommunications Conference, Globcom ’99<\/i>, Rio de Janeiro, BRAZIL, December 1999.<\/li>\n<\/ol>\n<\/li>\n<\/ol>\n

                  2000 to 2004<\/strong><\/p>\n

                    \n
                  1. \n
                      \n
                    1. D. Markovic, B. Nikolic, V.G. Oklobdzija,\u00a0“General Method in Synthesis of Pass-Transistor Circuits”<\/a>,\u00a022nd International IEEE Conference on Microelectronics<\/i>, May, 2000, Nis, Yugoslavia.<\/li>\n
                    2. B. Nikolic, V. G. Oklobdzija, V. Stojanovic, W. Jia, J. Chiu, M. Leung,\u00a0“Improved Sense Amplifier-Based Flip-Flop: Design and Measurements”<\/a>,\u00a0IEEE Journal of Solid-State Circuits<\/i>, Vol. 35, No. 6, June 2000.<\/li>\n
                    3. V. G. Oklobdzija, A. A. Farooqui,\u00a0“Computer Arithmetic for the Processing of Media Signals”<\/a>,\u00a0Invited Paper, Proceedings of SPIE Vol. 4116, Advanced Signal Processing Algorithms, Architectures, and Implementations<\/i>, San Diego, California, USA, 2 -4 August, 2000.<\/li>\n
                    4. D. Maksimovic, V. G. Oklobdzija, B. Nikolic, K. W. Current,\u00a0“Clocked CMOS Adiabatic Logic with Integrated Single-Phase Power-Clock Supply”<\/a>,\u00a0IEEE Transactions on VLSI Systems<\/i>, Vol. 8, No. 4, August 2000.<\/li>\n
                    5. A. Farooqui, K. W. Current, V. G. Oklobdzija,\u00a0“Partitioned Branch Condition Resolution Logic”<\/a>,\u00a0Proceedings of the Symposium on Integrated Circuits and Systems Design, SBCCI2000<\/i>, Manaus, Brazil, September 18-22, 2000.<\/li>\n
                    6. N. Nedovic, V. G. Oklobdzija,\u00a0“Hybrid Latch Flip-Flop with Improved Power Efficiency”<\/a>,\u00a0Proceedings of the Symposium on Integrated Circuits and Systems Design, SBCCI2000<\/i>, Manaus, Brazil, September 18-22, 2000.<\/li>\n
                    7. N. Nedovic, V. G. Oklobdzija,\u00a0“Dynamic Flip-Flop with Improved Power”<\/a>,\u00a0Proceedings of the 26th European Solid-State Circuits Conference, ESSCIRC 2000<\/i>, Stockholm, Sweden, September 19-21, 2000.<\/li>\n
                    8. N. Nedovic, V. G. Oklobdzija,\u00a0“Dynamic Flip-Flop with Improved Power”<\/a>,\u00a0Proceedings of the International Conference on Computer Design, ICCD 2000<\/i>, Austin, Texas, September 18-20, 2000.<\/li>\n
                    9. A. Farooqui, V. G. Oklobdzija,\u00a0“Impact of Architecture Extensions for Media Signal Processing on Data-Path Organization”<\/a>,\u00a034th Annual Asilomar Conference on signals, Systems and Computers<\/i>, Pacific Grove, California, October 29 – November 1, 2000.<\/li>\n
                    10. A. Farooqui, V. G. Oklobdzija,\u00a0“A Programmable Data-Path for MPEG-4 and Natural Hybrid Video Coding”<\/a>,\u00a034th Annual Asilomar Conference on signals, Systems and Computers<\/i>, Pacific Grove, California, October 29 – November 1, 2000.<\/li>\n
                    11. V. G. Oklobdzija,\u00a0“Computational Requirements for Media Signal Processing”<\/a>,\u00a034th Annual Asilomar Conference on signals, Systems and Computers<\/i>, Pacific Grove, California, October 29 – November 1, 2000.<\/li>\n
                    12. D. Markovic, B. Nikolic, V.G. Oklobdzija,\u00a0“General Method in Synthesis of Pass-Transistor Circuits”<\/a>,\u00a0Microelectronics Journal, Elsevier Science Publishing<\/i>, No. 31, November-December, 2000, p.991-998.<\/li>\n
                    13. A. Inoue, V. G. Oklobdzija, W. W. Walker, M. Kai, T. Izawa,\u00a0“A Low Power SOI Adder Using Reduced-Swing Charge Recycling Circuits”<\/a>,\u00a02001 IEEE International Solid-State Circuits Conference Digest of Technical papers<\/i>, San Francisco, February 2001.<\/li>\n
                    14. N. Nedovic, V. G. Oklobdzija, M. Leung,\u00a0“FIR Filter for Adaptive Equalization in PRML Read Channels”<\/a>,\u00a0The 5th World Multi-Conference on Systemics, Cybernetics and Informatics SCI 2001<\/i>, Orlando, Florida, July 22-25, 2001.<\/li>\n
                    15. H. Q. Dao, K. Nowka, V. G. Oklobdzija,\u00a0“Analysis of Clocked Timing Elements for DVS Effects over Process Parameter Variation”<\/a>,\u00a0Proceedings of the International Symposium on Low Power Electronics and Design<\/i>, Huntington Beach, California, August 6-7, 2001.<\/li>\n
                    16. N. Nedovic, M. Aleksic, V. G. Oklobdzija,\u00a0“Conditional Techniques for Low Power Consumption Flip-Flops”<\/a>,\u00a0Proceedings of the 8th IEEE International Conference on Electronics, Circuits and Systems<\/i>, Malta, September 2-5, 2001.<\/li>\n
                    17. N. Nedovic, M. Aleksic, V. G. Oklobdzija,\u00a0“Timing Characterization of Dual-Edge Triggered Flip-Flops”<\/a>,\u00a0Proceedings of the International Conference on Computer Design, ICCD 2001<\/i>, Austin, Texas, September 23-26, 2001.<\/li>\n
                    18. H. Q. Dao, V. G. Oklobdzija,\u00a0“Application of Logical Effort on Delay Analysis of 64-bit Static Carry-Lookahead Adder”<\/a>,\u00a035th Annual Asilomar Conference on Signals, Systems and Computers<\/i>, Pacific Grove, California, November 4-7, 2001.<\/li>\n
                    19. X. Y. Yu, V. G. Oklobdzija, W. W. Walker,\u00a0“Application of Logical Effort on Design of Arithmetic Blocks”<\/a>,\u00a035th Annual Asilomar Conference on Signals, Systems and Computers<\/i>, Pacific Grove, California, November 4-7, 2001.<\/li>\n
                    20. H. Q. Dao, V. G. Oklobdzija,\u00a0“Application of Logical Effort Techniques for Speed Optimization and Analysis of Representative Adders”<\/a>,\u00a035th Annual Asilomar Conference on Signals, Systems and Computers<\/i>, Pacific Grove, California, November 4-7, 2001<\/li>\n
                    21. C. Cuche, C. Piguet, V. G. Oklobdzija,\u00a0“Design Flow and CAD Tools for Asynchronous Design of Sequential Library Cells”<\/a>,\u00a0Second Working Group on Asynchronous Circuit Design (ACiD-WG) Workshop of the European Commission’s Fifth Framework Programme<\/i>, Munich, Germany, 28-29 January, 2002.<\/li>\n
                    22. M. Saint-Laurent, V. G. Oklobdzija, S. S. Singh, M. Swaminathan, J. D. Meindl,\u00a0“Optimal Sequencing Energy Allocation for CMOS Integrated Systems”<\/a>,\u00a03rd International Symposium on Quality Electronic Design<\/i>, San Jose, California, March 18-20, 2002.<\/li>\n
                    23. V. G. Oklobdzija,\u00a0“Clocking in Multi-GHz Environment”<\/a>,\u00a02002 23rd International Conference on Microelectronics.<\/i>\u00a0Proceedings (Cat. No.02TH8595). IEEE. Part vol.2, 2002, pp. 561-8 vol.2. Piscataway, NJ, USA.<\/li>\n
                    24. V. G. Oklobdzija,\u00a0“Clocking in Multi-GHz Environment”<\/a>,\u00a0Electrical Engineering Series, Facta Universitatis<\/i>, Nis, Vol. 15, No. 1. April 2002. (reprint from\u00a023rd International Conference on Microelectronics. Proceedings, 2002<\/i>)<\/li>\n
                    25. N. Nedovic, M. Aleksic, V. G. Oklobdzija,\u00a0“Comparative Analysis of Double-Edge versus Single-Edge Triggered Clocked Storage Elements”<\/a>,\u00a02002 IEEE International Symposium on Circuits and Systems<\/i>, Scottsdale, Arizona, May 26-29, 2002.<\/li>\n
                    26. N. Nedovic, M. Aleksic, V. G. Oklobdzija,\u00a0“Conditional Pre-Charge Techniques for Power-Efficient Dual-Edge Clocking”<\/a>,\u00a0Proceedings of the International Symposium on Low-Power Electronics and Design<\/i>, Monterey, California, August 12-14, 2002.<\/li>\n
                    27. V. G. Oklobdzija, J. Sparso,\u00a0“Future Directions in Clocking Multi-GHz Systems”<\/a>,\u00a0ISLPED’02: Proceedings of the 2002 International Symposium on Lower Power Electronics and Design<\/i>\u00a0(IEEE Cat. No.02TH8643). ACM. 2002, pp. 219. New York, NY, USA.<\/li>\n
                    28. H. Q. Dao, V. G. Oklobdzija,\u00a0“Performance Comparison of VLSI Adders Using Logical Effort”<\/a>,\u00a012th<\/sup>\u00a0International Workshop on Power And Timing Modeling, Optimization and Simulation<\/i>, Sevilla, SPAIN, September 11-13, 2002.<\/li>\n
                    29. V. G. Oklobdzija,\u00a0“Clocking and Clocked Storage Elements in Multi-GHz Environment”<\/a>,\u00a0Invited paper, 12th<\/sup>\u00a0International Workshop on Power And Timing Modeling, Optimization and Simulation<\/i>, Sevilla, SPAIN, September 11-13, 2002.<\/li>\n
                    30. N. Nedovic, W. W. Walker, V. G. Oklobdzija, M. Aleksic,\u00a0“A Low Power Symmetrically Pulsed Dual Edge-Triggered Flip-Flop”<\/a>,\u00a0Proceedings of the 28th<\/sup>\u00a0European Solid-State Circuits Conference<\/i>, Florence, ITALY, September 24-26, 2002.<\/li>\n
                    31. N. Nedovic, V. G. Oklobdzija, W. W. Walker,\u00a0“A Clock Skew Absorbing Flip-Flop”<\/a>,\u00a02003 IEEE International Solid-State Circuits Conference Digest of Technical papers<\/i>, San Francisco, February 2003.<\/li>\n
                    32. A. A. Farooqui, V. G. Oklobdzija, S. M. Sait,\u00a0“Area-Time Optimal Adder with Relative Placement Generator”<\/a>,\u00a0International Symposium on Circuits and Systems<\/i>, Bangkok, Thailand, May 25-28, 2003.<\/li>\n
                    33. X. Y. Yu, V. G. Oklobdzija, W. W. Walker,\u00a0“An Efficient Transistor Optimizer for Custom Circuits”<\/a>,\u00a0International Symposium on Circuits and Systems<\/i>, Bangkok, Thailand, May 25-28, 2003.<\/li>\n
                    34. B. R. Zeydel, V.G. Oklobdzija, S. Mathew, R.K. Krishnamurthy, S. Borkar,\u00a0“A 90nm 1GHz 22mW 16×16-bit 2’s Complement Multiplier for Wireless Baseband”<\/a>,\u00a0Proceedings of the 2003 Symposium on VLSI Circuits<\/i>, Kyoto, JAPAN, June 12 – 14, 2003.<\/li>\n
                    35. V. G. Oklobdzija, B. R. Zeydel, H. Q. Dao, S. Mathew, R. Krishnamurthy,\u00a0“Energy-Delay Estimation Technique for High-Performance Microprocessor VLSI Adders”<\/a>,\u00a0Proceedings of the International Symposium on Computer Arithmetic, ARITH-16,\u00a0<\/i>Santiago de Compostela, SPAIN, June 15-18, 2003<\/li>\n
                    36. H. Q. Dao, B. R. Zeydel, V. G. Oklobdzija, “Energy Minimization Method for Optimal Energy-Delay Extraction”,\u00a0Proceedings of the European Solid-State Circuits Conference<\/i>, ESSCIRC 2003, Estoril, PORTUGAL, September 16-18, 2003.<\/li>\n
                    37. H. Q. Dao, B. R. Zeydel, V. G. Oklobdzija, “Energy Optimization of High-Performance Circuits”,\u00a0Proceedings of the 13th International Workshop on Power And Timing Modeling, Optimization and Simulation<\/i>, Torino, Italy, September 10-12, 2003.<\/li>\n
                    38. V. G. Oklobdzija,\u00a0“Clocking and Clocked Storage Elements in a Multi-Gigahertz Environment”<\/a>,\u00a0IBM Journal of Research and Development<\/i>, Vol. 47, No. 5\/6, pp. 567-584, September\/November 2003.<\/li>\n
                    39. V. G. Oklobdzija,\u00a0“Multi-GHz Systems Clocking”<\/a>,\u00a0Invited Paper, Proceedings of the 5th International Conference on ASIC<\/i>, Beijing, P.R. China, October 22-24, 2003.<\/li>\n
                    40. V. G. Oklobdzija, “Issues in System on the Chip Clocking”,\u00a0Invited Paper, Proceedings of the IEEK System on Chip Design Conference<\/i>, Seoul, Korea, November 5-6, 2003.<\/li>\n
                    41. M. Vratonjic, B. R. Zeydel, H. Q. Dao, V. G. Oklobdzija,\u00a0“Low-Power Aspects of Different Adder Topologies”<\/a>,\u00a037th Annual Asilomar Conference on Signals, Systems and Computers<\/i>, Pacific Grove, California, November 9-12, 2003.<\/li>\n
                    42. N. Nedovic, W. W. Walker, V. G. Oklobdzija,\u00a0“A Test Circuit for Measurement of Clocked Storage Element Characteristics”<\/a>,\u00a0IEEE Journal of Solid-State Circuits<\/i>, Vol. 39, No. 8, pp. 1294-1304, August 2004.<\/li>\n<\/ol>\n<\/li>\n<\/ol>\n

                      2005 – 2010<\/strong><\/p>\n

                        \n
                      1. \n
                          \n
                        1. H. Q. Dao, B. R. Zeydel, V. Zyuban, V. G. Oklobdzija, “A Method for Energy Optimization of Digital Pipelined Systems”,\u00a0The Fourth Annual IBM Austin Conference on Energy-Efficient Design<\/i>, ACEED 2005, Austin, Texas, March 1-3, 2005.<\/li>\n
                        2. N. Nedovic, V. G. Oklobdzija,\u00a0“Dual-Edge Triggered Storage Elements and Clocking Strategy for Low-Power Systems”<\/a>,\u00a0IEEE Transaction on VLSI Systems<\/i>, Volume 13, Issue 5, pp. 577-590, May 2005.<\/li>\n
                        3. V. G. Oklobdzija, B. R. Zeydel, H. Q. Dao, S. Mathew, R. Krishnamurthy,\u00a0“Comparison of High-Performance VLSI Adders in Energy-Delay Space”<\/a>,\u00a0IEEE Transaction on VLSI Systems<\/i>, Volume 13, Issue 6, pp. 754-758, June 2005.<\/li>\n
                        4. B.R. Zeydel, T.T.J.H. Kluter, V. G. Oklobdzija,\u00a0“Efficient Energy-Delay Mapping of Addition Recurrence Algorithms in CMOS”<\/a>,\u00a0International Symposium on Computer Arithmetic, ARITH-17,\u00a0<\/i>Cape Cod, Massachusetts, USA, June 27-29, 2005.<\/li>\n
                        5. M. Aleksic, N. Nedovic, K. W. Current, V. G. Oklobdzija,\u00a0“A New Model for Timing Jitter Caused by Device Noise in Current-Mode Logic Frequency Dividers”<\/a>,\u00a0in Proc. of the 15th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS),\u00a0<\/i>Leuven, Belgium, September 21-23, 2005.<\/li>\n
                        6. H. Q. Dao, B. R. Zeydel, V. G. Oklobdzija,\u00a0“Architectural Considerations for Energy Efficiency”<\/a>,\u00a0Proceedings of the International Conference on Computer Design, ICCD 2005,\u00a0<\/i>San Jose, California, October 2-5, 2005.<\/li>\n
                        7. M. Vratonjic, B. R. Zeydel, V. G. Oklobdzija,\u00a0“Low- and Ultra Low-Power Arithmetic Units: Design and Comparison”<\/a>,\u00a0Proceedings of the International Conference on Computer Design, ICCD 2005,\u00a0<\/i>San Jose, California, October 2-5, 2005.<\/li>\n
                        8. H. Q. Dao, B. R. Zeydel, V. G. Oklobdzija,\u00a0“Energy-Efficient Optimization of the Viterbi ACS Unit Architecture”<\/a>,\u00a0Proceedings of the Asian Solid-State Circuit Conference, A-SSCC 2005,\u00a0<\/i>Hsinchu, Taiwan, November 1-3, 2005.<\/li>\n
                        9. S. K. Hsu, S. K. Mathew, M. A. Anders, B. R. Zeydel, V. G. Oklobdzija, R. K. Krishnamurthy, S. Y. Borkar,\u00a0“A 110 GOPS\/W 16-bit Multiplier and Reconfigurable PLA Loop in 90-nm CMOS”<\/a>,\u00a0IEEE Journal of Solid-State Circuits,\u00a0<\/i>Vol. 41, No. 1, pp. 256-264, January 2006.<\/li>\n
                        10. H. Q. Dao, B. R. Zeydel, V. G. Oklobdzija,\u00a0“Energy Optimization of Pipelined Digital Systems Using Circuit Sizing and Supply Scaling”<\/a>,\u00a0IEEE Transaction on VLSI Systems,<\/i>Vol. 14, Issue 2, Feb. 2006 pp. 122-134.<\/li>\n
                        11. C. Giacomotto, N. Nedovic, V. G. Oklobdzija,\u00a0“Energy-Delay Space Analysis for Clocked Storage Elements under Process Variations”<\/a>,\u00a016th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS),\u00a0<\/i>Montpellier, France Sept. 13-15, 2006.<\/li>\n
                        12. B. R. Zeydel, V. G. Oklobdzija,\u00a0“Methodology for Energy-Efficient Digital Circuit Sizing: Important Issues and Design Limitations”<\/a>,\u00a016th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS),\u00a0<\/i>Montpellier, France Sept. 13-15, 2006.<\/li>\n
                        13. M. Vratonjic, B. R. Zeydel, V. G. Oklobdzija,\u00a0“Circuit Sizing and Supply-Voltage Selection for Low-Power Digital Circuit Design”<\/a>,\u00a016th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS),\u00a0<\/i>Montpellier, France Sept. 13-15, 2006.<\/li>\n
                        14. X. Y. Yu, R. Montoye, K. Nowka, B. Zeydel, V. Oklobdzija,\u00a0“Circuit Design Style for Energy Efficiency: LSDL and Compound Domino”<\/a>,\u00a016th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS),\u00a0<\/i>Montpellier, France Sept. 13-15, 2006.<\/li>\n
                        15. C. Giacomotto, N. Nikola, V. Oklobdzija,\u00a0“The Effect of the System Specification on the Optimal Selection of Clocked Storage Elements”<\/a>,\u00a0IEEE Journal of Solid-State Circuits,\u00a0<\/i>Vol. 42, No. 6, pp. 1392-1404, June 2007.<\/li>\n
                        16. M. Singh, C. Giacomotto, B. R. Zeydel, V. Oklobdzija,\u00a0“Logic Style Comparison for Ultra Low Power Operation in 65nm Technology”<\/a>,\u00a017th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS),\u00a0<\/i>Gothenburg, Sweden Sept. 3-5, 2007 .<\/li>\n
                        17. C. Giacomotto, M. Singh, M. Vratonjic, V. Oklobdzija,\u00a0“Energy Efficiency of Power-Gating in Low-Power Clocked Storage Elements”<\/a>,\u00a018th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS),\u00a0<\/i>Lisbon, Portugal Sept. 10-12, 2008 .<\/li>\n
                        18. M. Aleksic, K. W. Current, V. G. Oklobdzija, “Jitter Analysis of Non-Autonomous MOS Current-Mode Logic Circuits<\/a>”\u00a0IEEE Transaction on Circuits and Systems I, Special Issue, Vol. 55, No.10, November 2008.<\/i><\/li>\n
                        19. D. Baran, M. Aktan, H. Karimiyan, V. G. Oklobdzija, “Exploration of Switching Activity Behavior of Addition Algorithms<\/a>“,\u00a0IEEE MWSCAS 2009<\/i>, Cancun, Mexico, 2-5 August 2009.<\/li>\n
                        20. Joosik Moon, Mustafa Aktan, V. G. Oklobdzija, “Design Methodology for Clocked Storage Elements Robust to Process Variations<\/a>“,\u00a0CENICS 2009<\/i>, Sliema, Malta, 11-16 October 2009.<\/li>\n
                        21. D. Baran, M. Aktan,H. Karimiyan, V. G. Oklobdzija, “Switching Activity Calculation of VLSI Adders<\/a>“,\u00a0IEEE ASICON 2009<\/i>, Changsha, China, 20-23 October 2009.<\/li>\n
                        22. D. Baran, M. Aktan,H. Karimiyan, V. G. Oklobdzija, “Switching Activity Calculation of VLSI Adders<\/a>“,\u00a0IEEE ASICON 2009<\/i>, Changsha, China, 20-23 October 2009.<\/li>\n
                        23. Joosik Moon, Mustafa Aktan, V. G. Oklobdzija, “Clocked Storage Elements Robust to Process Variations<\/a>“,\u00a0IEEE ASICON 2009<\/i>, Changsha, China, 20-23 October 2009.<\/li>\n
                        24. H. K. Alidash, S. M. Sayedi, H. Saidi, and V. G. Oklobdzija, “Soft Error Filtered and Hardened Latch,<\/a>”\u00a0IEEE ASICON 2009<\/i>, Changsha, China, 20-23 October 2009.<\/li>\n
                        25. M. Aktan, S. Paramesvaran, J. Moon, and V. G. Oklobdzija, “Energy-Delay Space Exploration of Clocked Storage Elements Using Circuit Sizing,<\/a>”\u00a0the Austin conference on Integrated systems and Circuits (ACISC)<\/i>, Austin, 2009.<\/li>\n
                        26. H. K. Alidash and V. G. Oklobdzija, “Low-Power Soft Error Hardened Latch,<\/a>”\u00a0PATMOS 2009, 19th international Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)<\/i>, Delft, Holland, 2009.<\/li>\n
                        27. M. Vratonjic, M. Ziegler, G. D. Gristede, V. Zyuban, T. Mitchell, E. Cho, C. Visweswariah, V. G. Oklobdzija, “A New Methodology for Power-Aware Transistor Sizing: Free Power Recovery (FPR)<\/a>”\u00a0, PATMOS 2009, 19th international Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)<\/i>, Delft, Holland, 2009.<\/li>\n
                        28. H. Karimiyan Alidash and V. G. Oklobdzija., “Low-Power Soft Error Hardened Latch<\/a>“,\u00a0Journal Low Power Electronics<\/i>\u00a06, 218-226 (2010).<\/li>\n
                        29. B. R. Zeydel, D. Baran, V. G. Oklobdzija, “Energy Efficient Design of High-Performance VLSI Adders<\/a>\u00a0“,\u00a0IEEE Journal of Solid-State Circuits\u00a0<\/i>, Vol 45, Issue 6. June 2010.<\/li>\n
                        30. Baran, Dursun; Aktan, Mustafa; Oklobdzija, Vojin G.; “\u00a0Energy efficient implementation of parallel CMOS multipliers with improved compressors<\/a>,”\u00a0Low-Power Electronics and Design (ISLPED), 2010 ACM\/IEEE International Symposium on<\/i>, pp.147-152, 18-20 Aug. 2010.\n

                          2010 – on<\/strong><\/li>\n

                        31. Baran, Dursun; Aktan, Mustafa; Oklobdzija, Vojin G.; “Multiplier Structures for Low Power Applications in Deep-CMOS<\/a>,”\u00a0Proceedings of 2011 IEEE International Symposium on Circuits and Systems (ISCAS 2011)<\/i>, pp., 15-18 May. 2011.<\/li>\n
                        32. Aktan, Mustafa; Baran, Dursun; Oklobdzija, Vojin G.; “A Quick Method for Energy Optimized Gate Sizing of Digital Circuits,”\u00a0International Workshop, PATMOS 2011 on Power and Timing Modeling, Optimization, and Simulation<\/i>, Madrid, SPAIN, September 27, 2011.<\/li>\n
                        33. Hossein Karimiyan Alidash,\u00a0 Sayed Masoud Sayedi,\u00a0 Vojin G. Oklobdzija, ” Soft-Error Hardened Redundant Triggered Latch,” 4th Asia Symposium on Quality Electronic Design (ASQED), July 10-11, 2012.<\/li>\n
                        34. V.G. Oklobdzija, M. Aktan, Baran, \u00ef\u00bf\u00bdOptimal Transistor Sizing and Voltage Scaling for Minimal Energy use at Fixed Performance<\/i>\u00ef\u00bf\u00bd, 7th<\/sup>\u00a0Argentine School of Micro-Nanoelectronics, Technology and Applications (EAMTA 2012), Cordoba, Argentina, August 4-12, 2012.<\/li>\n
                        35. V. Nawathe, M. Aktan, L. Wang, V. G. Oklobdzija, \u00ef\u00bf\u00bdParallelism trade-offs for data-driven circuits<\/i>\u00ef\u00bf\u00bd, 7th<\/sup>\u00a0Argentine School of Micro-Nanoelectronics, Technology and Applications (EAMTA 2012), Cordoba, Argentina, August 4-12, 2012.<\/li>\n
                        36. M. Aktan, D. Baran, V.G. Oklobdzija, \u00ef\u00bf\u00bdMinimizing Energy by Achieving Optimal Sparseness in Parallel Adders\u00ef\u00bf\u00bd, Proceedings of the 22nd IEEE Symposium on Computer Arithmetic, Lyon, FRANCE, June 22-24, 2015.<\/li>\n<\/ol>\n<\/li>\n<\/ol>\n

                          Books:<\/h3>\n
                            \n
                          1. \n
                              \n
                            1. \n
                                \n
                              1. V. G. Oklobdzija,\u00a0“High-Performance System Design: Circuits and Logic”<\/a>, Book, IEEE Press, July, 1999.<\/li>\n
                              2. V. G. Oklobdzija,\u00a0“The Computer Engineering Handbook”<\/a>, CRC Press, December, 2001.<\/li>\n
                              3. V. G. Oklobdzija, V. Stojanovic, D. Markovic, N. Nedovic,\u00a0“Digital System Clocking, High-Performance and Low-Power Aspects”<\/a>, John Wiley, January 2003.<\/li>\n
                              4. V. G. Oklobdzija, R. K. Krishnamurthy,\u00a0“High-Performance Energy-Efficient Microprocessor Design”<\/a>, Springer, July 2006.<\/li>\n
                              5. V. G. Oklobdzija,\u00a0“Digital Systems and Applications”<\/a>, Taylor & Francis, Nov. 2007.<\/li>\n
                              6. V. G. Oklobdzija,\u00a0“Digital Design and Fabrication”<\/a>, Taylor & Francis, Nov. 2007.<\/li>\n<\/ol>\n<\/li>\n<\/ol>\n<\/li>\n<\/ol>\n

                                Book Chapters:<\/h3>\n
                                  \n
                                1. \n
                                    \n
                                  1. V. G. Oklobdzija, “Digital Arithmetic”,\u00a0Encyclopedia of Electrical Engineering<\/i>, Vol. 5, John Wiley publishing, pp. 411-418, 1998.<\/li>\n
                                  2. V. G. Oklobdzija,\u00a0“Reduced Instruction Set Computing”<\/a>,\u00a0Encyclopedia of Electrical Engineering<\/i>, Vol. 18, John Wiley publishing, pp. 342-351, 1998.<\/li>\n
                                  3. V. G. Oklobdzija, “Computer Organization: Architecture,”\u00a0The Engineering Handbook<\/i>, R. C. Dorf (Ed.), a Chapter, CRC Press, Inc., pp. 1434-1446, 1995.<\/li>\n
                                  4. V. G. Oklobdzija, “Computers”,\u00a0The Engineering Handbook<\/i>, R. C. Dorf (Ed.), Introduction into Computers, a Chapter, CRC Press, Inc., pp. 1430-1433, 1995.<\/li>\n
                                  5. V. G. Oklobdzija, “Digital Systems”,\u00a0The Engineering Handbook<\/i>, R. C. Dorf (Ed.), Introduction into Digital Systems, CRC Press, Inc., pp. 1286-1288, 1995.<\/li>\n
                                  6. V. G. Oklobdzija, “Computer Arithmetic”,\u00a0The Electrical Engineering Handbook<\/i>, R. C. Dorf (Ed.), a Chapter, CRC Press, Inc., pp. 1858-1865, 1993.<\/li>\n
                                  7. V. G. Oklobdzija, “High-Speed VLSI Arithmetic Units: Adders and Multipliers”, in “Design of High-Performance Microprocessor Circuits<\/i>“, Book Chapter, Book edited by A. Chandrakasan, IEEE Press, 2000.<\/li>\n
                                  8. V. G. Oklobdzija, “Clocking Multi-GHz Systems”,\u00a0Low-Power Electronics Design<\/i>, C. Piguet (Ed.), a Chapter, CRC Press, Inc, 2004.<\/li>\n
                                  9. B. R. Zeydel and V. G. Oklobdzija, “Design of energy-efficient digital circuits”,\u00a0High-Performance Energy-Efficient Microprocessor Design<\/i>, V. G. Oklobdzija and R. K. Krishnamurthy (Eds.), Springer, 2006.<\/li>\n
                                  10. V. G. Oklobdzija and B. R. Zeydel, “Energy-delay characteristics of CMOS adders”,\u00a0High-Performance Energy-Efficient Microprocessor Design<\/i>, V. G. Oklobdzija and R. K. Krishnamurthy (Eds.), Springer, 2006.<\/li>\n<\/ol>\n<\/li>\n<\/ol>\n<\/td>\n

<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

 <\/p>\n","protected":false},"excerpt":{"rendered":"

1970 to 1979 V. G. Oklobdzija and N. Konjevic,\u00a0“Spectroscopy Of Axisymmetric Plasma Sources”,\u00a0Proceedings of the Eleventh International Conference on Phenomena in Ionized Gases, p. 449, 1973. V. G. Oklobdzija and N. Konjevic,\u00a0“Refractive-Ray Bending In Axially-Symmetric Plasma Sources”,\u00a0Proceedings of the International Conference on the Physics of Ionized Gases, 1974. V. G. \u2026 Continue reading → <\/span><\/a><\/p>\n","protected":false},"author":3,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"open","template":"","meta":{"inline_featured_image":false,"ngg_post_thumbnail":0,"footnotes":""},"class_list":["post-17","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/faculty.engineering.ucdavis.edu\/oklobzija\/wp-json\/wp\/v2\/pages\/17","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/faculty.engineering.ucdavis.edu\/oklobzija\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/faculty.engineering.ucdavis.edu\/oklobzija\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/faculty.engineering.ucdavis.edu\/oklobzija\/wp-json\/wp\/v2\/users\/3"}],"replies":[{"embeddable":true,"href":"https:\/\/faculty.engineering.ucdavis.edu\/oklobzija\/wp-json\/wp\/v2\/comments?post=17"}],"version-history":[{"count":8,"href":"https:\/\/faculty.engineering.ucdavis.edu\/oklobzija\/wp-json\/wp\/v2\/pages\/17\/revisions"}],"predecessor-version":[{"id":250,"href":"https:\/\/faculty.engineering.ucdavis.edu\/oklobzija\/wp-json\/wp\/v2\/pages\/17\/revisions\/250"}],"wp:attachment":[{"href":"https:\/\/faculty.engineering.ucdavis.edu\/oklobzija\/wp-json\/wp\/v2\/media?parent=17"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}