My general research area is computer systems and I have worked on various aspects of hardware modeling, design, implementation, optimization, and applications. I have co-authored more than 130 papers in various IEEE and ACM sponsored conferences and journals. I am also a co-author of a book published by Morgan Claypool under the Synthesis Lectures Series on photonic interconnects in computer architecture.
Here is a summary of some of my key accomplishments.
- Asynchronous Design: As part of my Ph.D. dissertation I developed a hardware description language (called hopCP) and a high-level synthesis tool for asynchronous circuits. Subsequently I developed tools for power estimation and performance analysis of asynchronous circuits. Later at UC Davis, along with my students I developed a library for self-timed circuits, DCT processors, and the microarchitecture for one of the first asynchronous superscalar processor.
- Computer Architecture: We designed and evaluated tile-based multicore processors under the framework called Synchroscalar which was published in ISCA 2004. The main contribution of this work was understanding the trade-offs between the granularity of a tile (or core) and the power and performance. We were one of the early research groups (in 2008) to show the potential of WDM (wavelength division multiplexing) based optical interconnects to overcome the memory bottleneck in modern processors. We followed this up with the design of new topologies for on-chip photonic interconnects and a detailed study of resilience issues in micro-ring resonator based photonic networks. More recently, we demonstrated the potential of photonic interconnects in die-stacked systems.
- Optical Switches: In collaboration with the photonics group at UC Davis, we designed and implemented the control plane for an all optical packet switch based on label-switching. Light cannot be stored (unlike electronic signals) easily, so the lack of buffering makes the design of an all-optical switch challenging. We developed and implemented different contention resolution algorithms to address this challenge and demonstrated an all-optical switch based on AWGR (Arrayed Waveguide Grating Routers) for optical backbone networks in the first phase of the project and later we redesigned the switch for datacenter applications where latency and power consumption are additional constraints. Various aspects of the design and implementation are described in over 40 papers over the past 15 years.
- LDPC Codes: Over the past two decades LDPC codes are being widely used in many latency critical applications. ASIC implementations are fast but are not suitable in many applications especially where programmability is required. We developed reconfigurable decoders for LDPC codes based on vector-processing concepts to improve the throughput of LDPC codes with large codelengths. We extended this to non-binary LDPC codes and developed a platform for performance evaluation of LDPC codes down to bit error rates of 10^-14. This work is documented in 5 papers published in IEEE Transactions on Circuits and Systems and ACM Transactions on Reconfigurable Technology and Systems in 2011.
- Embedded Systems: We developed a methodology for power optimization of embedded software on mobile phones using Markov Decision Processes and collaborative bandwidth sharing based on user profiles. This work received a best paper nomination at the 2009 ACM International Symposium on Embedded Software (EMSOFT) and was invited for a demo contest at ACM ISLPED 2010. Subsequently this was extended to a general design methodology for long-term adaptation of embedded software on heterogeneous devices (like sensors nodes in infrastructure monitoring applications for example).