Selected Publications

  • J. Campos and H. Al-Asaad, “A novel mutation-based validation paradigm for high-level hardware descriptions”, to appear in IEEE Transactions on VLSI, 2008.
  • H. Al-Asaad, “Efficient global fault collapsing for combinational library modules”, Proc. International Conference on Computer Design (CDES), 2007, pp. 37-43.
  • J. Campos and H. Al-Asaad, “Concurrent design error simulation for high-level microprocessor implementations”, Proc. Autotestcon, 2004, pp. 382-388.
  • H. Al-Asaad and J. P. Hayes, “Logic design verification via simulation and automatic test pattern generation”, Journal of Electronic Testing: Theory and Applications, Vol. 16, No. 6, pp. 575-589, December 2000.
  • H. Al-Asaad and J. P. Hayes, “ESIM: A multimodel design error and fault simulator for logic circuits”, Proc. VLSI Test Symposium, 2000, pp. 221-228.

Comments are closed.