Research Interests

Selected Projects:

 

Fundamental Limitations of Circuit Architectures: We develop theoretical frameworks for analyzing the fundamental frequency, power and noise limitations of various circuit architectures and exploit the results to design novel circuits with significantly better performance. Broadly speaking, the main innovation here is the introduction of a systematic methodology for designing circuits operating at the limits of the transistors in any given process. This is achieved by blending device physics, circuit theory, and high frequency circuit design into a coherent technique. In the context of signal generation, this method led to the implementation of a 482 GHz oscillator in a 65 nm CMOS process with an output power of 160 µW. In signal amplification domain, an amplifier was implemented with 9.2dB of gain at 260GHz in a 65nm CMOS process with fmax of ~320 GHz. This project is an example of looking into circuit design from a completely different angle to achieve what is otherwise impossible.

260GHz amplifier with 9.2dB gain in 65nm CMOS process

260GHz amplifier with 9.2dB gain in 65nm CMOS process

480 GHz oscillator with -7.9 dBm power in 65 nm CMOS

480 GHz oscillator with -7.9 dBm power in 65 nm CMOS

 

Going Beyond the Conventional Limitations of Passive Circuits: We have introduced a methodology to perform high performance signal processing using 2-D electrical lattices. Using the anisotropic behavior of these lattices, we proposed an Electrical Prism that can achieve a filtering quality factor, which is orders of magnitude larger than the quality factor of the individual components in terahertz frequencies. An Electrical Prism with quality factor of 420 at 460 GHz consisting of elements with the quality factor 20 was presented.

Electrical prism in a 130 nm CMOS

Electrical prism in 130 nm CMOS

 

Traveling-Wave Circuits for Wide Band Signal Generation: Inspired by the Doppler effect and using the traveling-wave properties, we proposed a novel wideband frequency multiplier that efficiently generates and combines the harmonics of the input signal. The implemented frequency doubler operates from 220 GHz to 275 GHz in a 65 nm CMOS process with an output power of -6.6 dBm at 244 GHz.

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220 GHz to 275 GHz frequency multiplier in 65 nm CMOS

 

Terahertz System-on-Chip: Not too long ago, envisioning a CMOS terahertz system-on-chip did not seem realistic. This is changing thanks to innovative circuit design methodologies and transistor scaling. For the first time, we have introduced a CMOS terahertz source that generates a useful amount of power for most terahertz applications. Other CMOS terahertz system blocks for signal amplification, signal processing (electrical prism), and signal synthesis (frequency multiplier) were also proposed. Our group is working toward implementing different building blocks and innovative system architectures for a THz system.

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